In order to analyze the line image sticking of TFT-LCD, the influence of pattern’s data driving voltage on common voltage through capacitance (CDC) is studied. Firstly, according to the actual film distribution of array, the specific composition of capacitance in the film is described, and the equivalent circuit model of CDC is established. The CDC in actual working state is measured, and analyzed by the model effectively. Then, the method is established to measure the distortion of common voltage generated by checkerboard driving voltage and analyze the mechanism of line image sticking. Finally, the “black-gray-bar” pattern is set to maximize distortion, so as to analyze the formation process and influencing factors of distortion. The experimental results show that when TFT is turned off, TFT presents a high resistance state, CDC is the same as C0 (corresponding to overlapping metal line of data voltage and common voltage), which is 55 fF. When the TFT is turned on, it presents a low resistance state, CDC is connected in parallel by a storage capacitance and C0, which is 530 fF. When the TFT is in the intermediate state, the capacitance is the intermediate value obtained from the measure. The larger the capacitance of CDC is, the faster the conversion speed of data voltage is, and the larger the distortion is. It is found that reducing the conversion speed from 48 ns to 53 ns can reduce the distortion value from 2.67 V to 2.61 V.