State of polarization (SOP), as the fundamental property of light, has been extensively studied and utilized for various applications, such as telecommunications [1,2], optical coherence tomography [3], medical diagnosis [4], light remote detection and ranging (lidar) [5,6], and material analysis [7]. The polarization-controlling devices have been heavily investigated as the crucial role in polarization management. Traditionally, polarization management is often achieved by mechanically rotating the wave plates or utilizing the fiber-squeezing birefringence effect [8,9]. Unfortunately, they are bulky, low-speed, and poorly programmable/reconfigurable.

As an alternative, on-chip polarization controllers (PCs) are becoming more and more attractive and feasible because integrated photonics has been developed very successfully with various materials platforms in the past decades [10,11]. In particular, silicon, InP, SiN, and thin-film lithium niobate photonic waveguides with ultrahigh index contrasts usually offer high birefringence and thus provide extremely powerful options for realizing on-chip polarization-handling devices [12–14]. Currently, various high-performance on-chip polarization-handling devices have been realized successfully, including polarization rotators [15–17], polarization beam splitters [18–20], and polarization splitting rotators (PSRs) [21–24]. Moreover, on-chip PCs have also been developed by utilizing the thermo-optic effect [25], the carrier dispersion effect [26], and the electro-optic effect [27], featuring the excellence of reconfigurability, high-speed operation, and low-power dissipation. With high-performance PCs, one can realize the generation/conversion of SOP [25,27–31], automatic polarization calibration [32,33], polarization scrambling [27], and polarization measurement [26,27,34], which have been playing a vital role in many scenarios such as optical communication [35], optical sensing [36,37], and quantum technology [29,38,39].

Generally speaking, there are mainly two schemes to achieve on-chip polarization controlling. One is using the combination of PSRs and 2×2 Mach–Zehnder interferometers (MZIs) [31–33,40]. In these designs, the PSRs separate/combine the TE0 and TM0 modes, while the MZIs tune the polarization extinction ratio (PER) or the phase difference for the TE0 and TM0 modes. In Ref. [25], a silicon PC was proposed to achieve the conversion of two arbitrary SOPs. In order to eliminate the negative influence from the non-ideality of the PSRs and the 2×2 multimode interferometers (MMIs) used for the MZIs, five heaters were introduced for thermal-tuning. As a result, the total length is longer than ∼2500μm and the excess loss (EL) is higher than ∼4.5dB. Similarly, a PC based on thin-film lithium niobate photonic waveguides was also demonstrated with a PER range of 41.9 dB and an EL of ∼0.92dB [27]. This design still includes multistage MZIs, and thus the total length is as long as 4.5 cm. As an alternative, the combination of polarization rotators (PRs) and phase shifters (PSs) [28,30] provides another option for achieving on-chip polarization controlling. The PRs provide the ability to modify the PER, while the PS enables the controlling of the phase difference. In this way, the demonstrated PC exhibits a PER range of about 40 dB and a total length of >3000μm. Therefore, the realization of compact PCs with high performance is still challenging.

In this paper, we propose and demonstrate a compact and robust silicon-based on-chip PC that consists of a special polarization converter and two phase shifters (PSs). These two PSs are connected with the input and output ports of the polarization converter, respectively, to adjust the phase difference between the two orthogonal polarization modes (i.e., TE0 and TM0 modes). The special polarization converter is designed with a structure similar to our previous polarization switch used for switching the TE0 and TM0 modes [41], and it consists of a 1×1MZI integrated with two polarization-dependent mode converters (PDMCs) at the input/output ends. In particular, the 1×1MZI is configured with two thermally tunable PSs embedded in its arms and two 1×2 dual-mode 3-dB power splitters (DMPSs) based on a triple-core adiabatic taper [41]. When light with an arbitrary SOP is launched into the chip, the TE0 and TM0 modes are simultaneously excited with the corresponding PER and phase difference (depending on the initial SOP of light). The PER and the phase difference of the TE0/TM0 modes can be adjusted freely by tuning the three PSs so that the SOP of light emitted from the chip can be controlled flexibly. The fabricated PC has a footprint of ∼150μm×700μm, an on-chip EL of ∼1dB, and a record PER range of >54dB in the wavelength range of 1530–1620 nm. The present on-chip controller shows high performance regarding configuration compactness and controlling simplicity, which is very attractive and useful for further monolithic photonic integration in the future.

The electric vector motion trail of a plane light wave is described as the following form: {Ex=axe−i(ωt+δx)Ey=aye−i(ωt+δy),(1)in which Ex and Ey are the horizontal and vertical electrical components of the plane light wave, ax,y are their corresponding amplitudes, δx,y are their initial phases, ω is the angular frequency, and t is time. The light SOP is usually characterized by the PER defined as 10log10(ay2/ax2) and the phase difference δ0 given by δy−δx. It can be seen that the light SOP can be controlled freely when tuning the PER and the phase difference δ0.

Figure 1(a) shows the proposed on-chip PC, which consists of a special polarization converter, two PSs (i.e., PS #1 and PS #3), and two edge couplers. Particularly, the polarization converter consists of an MZI connected with two PDMCs (i.e., PDMC #1 and PDMC #2) at the input/output ends. Here the MZI is constructed with two 1×2 DMPSs (i.e., DMPS #1 and DMPS #2) and two thermally-tunable PSs (i.e., PS #2a and PS #2b) embedded in the MZI arms. With the PDMC based on the polarization-dependent mode hybridity [41,42], the launched TM0 mode is efficiently converted into the TE1 modes, while the launched TE0 mode is kept unchanged losslessly in theory. The DMPS is designed with a trident waveguide structure based on the principle of adiabatic mode evolution [41]. Accordingly, the TE0 mode is uniformly split into two TE0 modes with identical phases, while the TE1 mode is uniformly split into two TE0 modes with a phase difference of π. PS #2a and PS #2b are used to achieve the desired phase difference between these two TE0 modes propagating in the two MZI arms. Therefore, one can freely achieve a controllable TE0−TM0 mode conversion by utilizing such a special polarization converter. Meanwhile, PS #1 and PS #3 are inserted, respectively, to tune the phase difference between the TE0 and TM0 modes in the input/output sections as required. When light with an arbitrary SOP is launched into the chip, the TE0 and TM0 modes in the silicon photonic waveguide are excited, respectively. The TE0 mode passes through PS #1 and PDMC #1 almost losslessly, while the TM0 mode is efficiently converted to the TE1 mode by PDMC #1. Meanwhile, the TE0 and TE1 modes have some phase differences δ, depending on the waveguide birefringence and the thermal tuning of PS #1 (introducing a phase delay φ1). As a result, mode interference occurs when the TE0 and TE1 modes pass through the DMPS #1 simultaneously, and the power ratio and the phase difference of the two split TE0 modes are determined by that of the TE0 and TE1 modes. These two TE0 modes enter the MZI arms (arm #1 and arm #2), and their phase difference is further tuned by PS #2 (with an addition of φ2). After passing through DMPS #2, one can acquire the TE0 and TE1 modes with an adjustable power ratio and phase difference. Then the TE1 mode is converted to the TM0 mode, while the TE0 mode is kept unchanged by using PDMC #2. Finally, the phase difference of the TE0 and TM0 modes at the output port can flexibly be tuned as desired by tuning PS #3 to generate any SOP in the output fiber or the free space. With the transmission matrix of the whole chip, the output field [Ex′,Ey′]T (defined by the amplitudes [ax′,ay′] and the phase difference δ′) is related to the input field [Ex,Ey]T (defined by the amplitudes [ax,ay] and the phase difference δ0) with the following equation: [Ex′Ey′]=CP3CPCCP1[ExEy],(2)in which CP1,CPC, and CP3 are the transmission matrices of PS #1, the polarization converter, and PS #3. They are given as CP1=[100e−i(φ1+δ1)],(3)CPC=12[1+e−iφ2−e−iδ22+e−i(φ2+δ22)−e−iδ22+e−i(φ2+δ22)e−iδ2+e−i(φ2+δ2)],(4)CP3=[100e−i(φ3+δ3)],(5)where φ1,φ2, and φ3 are, respectively, the phase changes induced by the parts of PS #1, the polarization converter, and PS #3; δ1,δ2, and δ3 are the phase differences induced by the waveguide birefringence in these three parts.

With the transmission matrix given above, the performance of the proposed PC can be evaluated clearly. For the sake of simplicity, we set δ1,2,3 to be 0 in the following discussion. When the x-polarized light (i.e., the TE0 mode) or y-polarized light (i.e., the TM0 mode) is launched, the PER can be tuned by adjusting PS #2 only (depending on the phase shifting φ2). Here we consider the case with the TE0 mode (which has [ax2,ay2,δ0]=[1,0,0]) as an example. Figure 2(a) shows the normalized results of ax2 and ay2 for the output field as the phase shifting φ2 varies from 0 to 2π. It can be seen that arbitrary ax2 and ay2 can be achieved in the range of [0,1]. Figure 2(b) shows the calculated phase difference δ′ for the output field when the phase-shifting φ3 is 0, having two discrete values of 1.5π and 0.5π. When tuning the phase-shifting φ3, arbitrary phase difference δ′ can also be achieved for the output field. As a result, one can traverse the Poincaré sphere as the phase-shiftings φ2 and φ3 are tuned in the range of [0, 2π], as shown in Fig. 2(c). Here the SOP is described with normalized Stokes parameters, i.e., S1,S2, and S3, which are defined as {S1=ax2−ay2S2=2axaycosδS3=2axaysinδ.(6)

Another example considered here is the case when the input light is 45°-polarized (i.e., [ax2,ay2,δ0]=[1/2,1/2,0]). Figures 2(d) and 2(e) show the calculated results of the normalized power ax2 and ay2, and the phase difference for the output field as the phase shifting φ2 varies from 0 to 2π. Here the phase-shifting φ1 is assumed to be 0, 0.2π, or 0.5π. When φ1=0, one always has ax′2=ay′2=1/2 and δ′=0, which is independent of the phase-shifting φ2, indicating the polarization converter is unable to tune the light SOP. When choosing φ1=0.2π, the normalized power can be tuned in the range of [0.2, 0.8] and it is still unable to achieve an arbitrary power range of [0,1]. Instead, when choosing φ1=π/2, a normalized power range of [0,1] can be achieved, as shown in Fig. 2(d). The corresponding phase difference δ′ is shown in Fig. 2(e). As a result, for the 45°-polarized input light, one can traverse the Poincaré sphere by fixing φ1=0.5π and scanning φ2 and φ3 in the range of [0, 2π], as shown in Fig. 2(f).

According to the transmission matrix given in Eq. (2), the phase difference between the TE0 and TM0 modes should be chosen as δ=δ0+δ1+φ1=2π±0.5π, thus making sure that ax2 and ay2 can be tuned from 0 to 1. For example, for the launched light beam with [ax2,ay2,δ0]=[0.25,0.75,0.25π], Figs. 2(g) and 2(h) show the calculated normalized power ax′2 and ay′2 and the phase difference δ′ for the output field as the phase-shifting φ2 varies from 0 to 2π. Here the phase-shifting φ1 is assumed to be 0.25π, 0.75π, and 1.25π. It can be seen that ax′2 and ay′2 can cover the range of [0,1] by tuning φ2 when φ1 is set to be 0.25π or 1.25π, while for φ1=0.75π, the tuning range covers [0.25, 0.75] only. The calculated corresponding δ′ is shown in Fig. 2(h). By fixing φ1=0.25π or 1.25π, and scanning φ2 and φ3 in the range of [0, 2π], one can also traverse the Poincaré sphere for the launched light beam [ax2,ay2,δ0]=[0.25,0.75,0.25π], as shown in Fig. 2(i).

In order to realize the on-chip PC, here we use an SOI wafer with a 220-nm-thick top silicon core layer (i.e., hc=220nm) and a 2-μm-thick buried oxide layer (i.e., hb=2μm). Figure 1(b) shows the cross section of the fully etched silicon photonic waveguide, which has a silica upper cladding with a thickness of hcl=2.2μm and a 300-nm-thick Cr/Au heater embedded in the upper cladding. The simulated field profiles of the TE0 and TM0 modes in a 400-nm-wide silicon photonic waveguide are given in Fig. 3(a) as an example, showing that the TE0 mode is more confined in the silicon core than the TM0 mode when wco>220nm. As a result, it is expected that the TE0 mode has a higher effective thermo-optic coefficient dNeff/dT than the TM0 mode because silicon has a much more significant thermo-optical coefficient than silica. Figure 3(b) shows the calculated results for the effective thermo-optic coefficients dNeff/dT of the TE0 and TM0 modes. It can be seen that the coefficient dNeff/dT of the TE0 mode increases from ∼1.43×10−4/°C to the maximum of ∼1.93×10−4/°C and then decreases to ∼1.82×10−4/°C eventually as the core width increases from 0.3 to 1.2 μm. In contrast, the coefficient dNeff/dT of the TM0 mode increases monotonously from ∼0.61×10−4/°C to the maximum of ∼1.35×10−4/°C. Accordingly, the difference between the coefficients dNeff/dT of the TE0 and TM0 modes is also given in Fig. 3(b), showing that there is a maximum of ∼1.02×10−4/°C achieved for the optimized core width wco=0.35μm. With this design, the power consumption of PS #1 and PS #3 can be minimized for achieving the target phase difference δ. On the other hand, the propagation loss for 0.35-μm-wide silicon photonic waveguides is usually high due to the scattering at the waveguide sidewalls [43]. Therefore, in this paper we choose the core width as wco=0.4μm (slightly wider than the optimal value 0.35 μm) for the sections of PS #1 and PS #3 for balancing between the propagation loss and the power consumption. In this case, the coefficients dNeff/dT of the TE0 and TM0 modes have a difference Δ(dNeff/dT) of about 1.0×10−4/°C, which is slightly lower than the maximum of 1.02×10−4/°C at wco=0.35μm. Accordingly, the maximal temperature increase is approximately 155°C to achieve a phase difference of 2π when the length of the heating section is chosen as 100 μm. Therefore, in this paper we choose the lengths of PS #1 and PS #3 to be 100 μm for compact footprints as well as a moderate heating temperature.

The PDMCs are designed by utilizing the mode hybridity in a bilevel waveguide taper, enabling the mode conversion from a fully etched strip waveguide to a shallowly etched ridge waveguide, as shown in Fig. 4(a). In this paper, the slab thickness for the ridge waveguide is chosen to be hs=70nm for implementing the desired mode hybridity and accommodating the standard foundry process as shown in Fig. 1(c). Figure 4(a) shows the calculated effective indices of the TE0, TM0, and TE1 modes of the bilevel ridge waveguide as the core width varies from 0.4 to 0.8 μm. It can be seen that there is a region around wco=0.53μm where the TM0−TE1 mode hybridity occurs. As a result, when the PDMC is designed by using an adiabatic bilevel taper with a core width gradually varying from 0.4 to 0.8 μm, the launched TM0 mode can be converted to the TE1 mode efficiently, as shown in Fig. 4(b), which is due to the mode hybridity [41]. In contrast, the TE0 mode passes through the PDMC losslessly, as shown in Fig. 4(c). Here the PDMC and DMPSs are designed with the parameters given in Ref. [41].

Figure 5(a) shows the simulated light propagation in the structure consisting of PS #1, PDMC #1, and DMPS #1 when the TE0 mode is launched as an example. It can be seen that the TE0 mode goes through PS #1 and PDMC #1 losslessly. Then it is split symmetrically and coupled to the two TE0 modes of two MZI arms by DMPS #1. In contrast, the launched TM0 mode is converted to the TE1 mode by PDMC #1 due to the mode hybridity. The TM1 mode is then split and coupled to the TE0 modes of the two MZI arms, which have a power ratio of 50%:50% and a phase difference of π, as shown in Fig. 5(b). Note that PS #1 does not introduce any modification to the light SOP for the TE0 or TM0 mode launched alone. Otherwise, for the light SOP with the TE0 and TM0 modes excited simultaneously, PS #1 plays a key role for the polarization conversion, as discussed earlier. For example, for the 45°-polarized light launched into the chip, the TE0 and TM0 modes are excited with equal power and zero phase difference, and the TM0 mode is further converted into the TE1 mode [see Fig. 5(b)]. In this case, the interference between the TE0 mode and the TE1 mode occurs, which depends on the phase difference δ between them. The TE0−TE1 mode interference finally determines the power splitting ratio of the DMPS for the TE0 modes in the MZI arms, indicating that the splitting ratio of DMPS #1 can be adjusted freely by tuning the phase-shifting φ1 of PS #1. For example, when phase difference δ=0, the power-splitting ratio of the DMPS is 0:100% and light is fully coupled to the TE0 mode in the upper MZI arm when operating at 1550 nm, as shown in Fig. 5(c). When δ=π, the power-splitting ratio of the DMPS is 100%: 0 and light is fully coupled to the TE0 mode in the lower MZI arm, as shown in Fig. 5(d). When δ=2mπ±π/2, the power-splitting ratio of the DMPS is about 50%:50%, as shown in Fig. 5(e). Similarly, it is always possible to achieve a power-splitting ratio of 50%:50% for any light SOP by tuning the phase-shifting δ. Note that the power-splitting ratio of 50%:50% is the key to achieving arbitrary SOP for the emitted light.

As a key role, PS #2 is used to tune the phase difference φ2 between the TE0 modes propagating along the two MZI arms, enabling the adjustment of the power ratio of the TE0 and TE1 modes at the output port of DMPS #2. The TE1 mode is then converted completely to the TM0 mode after going through PDMC #2. As a result, PS #2 actually plays the role of tuning the PER of the TE0 and TM0 modes at the output port. Figure 6 shows the simulated light propagation in the structure consisting of two MZI arms, DMPS #2, and PDMC #2. Here two TE0 modes with an initial phase difference of δ0=0 are launched into the two MZI arms. When φ2=0, these two TE0 modes finally are recombined and coupled to the TE0 mode at the output end of DMPS #2. Then the TE0 mode goes through PDMC #2 losslessly, as shown in Fig. 6(a). In contrast, when φ2=π, these two TE0 modes in the two MZI arms are combined to be the TE1 mode after passing DMPS #2, and finally the TE1 mode is converted to the TM0 mode at the output port by PDMC #2, as shown in Fig. 6(b). Figure 6(c) also shows the light propagation for the φ2=0.5π; the output TE0 and TM0 modes have a power ratio of 50%:50%.

The chip was fabricated with the standard 220-nm-thick SOI foundry process, and a two-step etching process was used to form the bilayer ridge waveguides. Figures 7(a) and 7(b) show the optical micrographs of the fabricated chip and the polarization converter, and Fig. 7(c) shows the scanning electron micrograph (SEM) of the DMPS. The fabricated chip was diced and polished for efficient fiber-chip edge coupling.

The fabricated PC was first measured using the experimental setup shown in Fig. 8. Light from the amplified spontaneous emission (ASE) source passes through a fiber inline polarizer and a fiber PC (PC) and finally enters the chip through the edge coupler. At the output side, the TE0 mode (Port #1) and the TM0 mode (Port #2) of the emitted light are separated with a fiber polarization beam splitter (PBS) and received by an optical spectrum analyzer (OSA). The three PSs are thermally tuned by injecting the currents to the corresponding microheaters connected with a multichannel voltage source (MVS) via a printed circuit board (PCB).

Figures 9(a)–9(d) show the measured spectra from output Port #1 and Port #2 when the TE0 or TM0 modes are selectively excited by controlling fiber PC from the input side. Here the results are normalized, with the spectrum of a straight waveguide fabricated on the same chip. The measured transmissions for the launched TE0 mode when PS #2 is at the off state (P2=0mW, φ2=0) are shown in Fig. 9(a). The TE0 mode has an EL less than 0.5 dB (blue line) and PER larger than 12 dB in the 1530–1605 nm wavelength range, and the largest PER is about 19 dB at 1542 nm wavelength. When PS #2 is on (P2=18.7mW, φ2=π), the TE0−TM0 mode conversion happens; the outputs of Port #1 and Port #2 are shown in Fig. 9(b). The TE0−TM0 conversion has an EL of ∼0.8dB and a PER larger than 15 dB at 1530–1605 nm, and the largest PER is ∼21dB at 1558 nm. The measured transmissions for the launched TM0 mode are shown in Figs. 9(c) and 9(d). When PS #2 is off, the TM0 mode has an on-chip EL less than ∼1dB and a PER larger than 12 dB in the spectral range of 1530–1605 nm, and the largest PER of 18 dB is achieved at 1568 nm. While PS #2 is on with a power of 18.7 mW, the TM0−TE0 conversion has an EL ∼0.6dB and a PER larger than 15 dB in the spectral range of 1530–1605 nm, and one has the largest PER of 22.5 dB at 1552 nm. As a result, the attainable PER range is >40dB for both TE0 and TM0 modes. It should be mentioned that the measured device PER range is limited by the fiber PBS used, which has a PER of 20 dB.

Figure 10 shows the experiment setup to demonstrate the generation of arbitrary SOPs for 1550 nm by using the present chip. Light from a tunable laser (TL) passes through a fiber PC and then is coupled to the chip. Light from the output port of the chip is collected through a 20× objective lens and finally is captured by using a charge coupled device (CCD). Here a quarter-wave plate (QWP) and a polarizer were used to test the SOP of the output light.

Figure 11(a) shows the captured free-space mode field profiles when the TE0 mode is launched. Here the phase difference φ2 introduced by PS #2 is tuned to be 0 or π. When setting φ2=0, a fundamental mode field profile is observed clearly by aligning the polarizer to be parallel to the x axis. Otherwise, when aligning the polarizer to be vertical to the x axis, nothing is observed. This indicates that the light emitted from the chip is the TE0 mode when φ2=0. In contrast, when setting φ2=π, a fundamental mode field profile is observed clearly by aligning the polarizer to be vertical to the x axis, indicating that the light SOP is converted successfully from the TE0 mode launched at the input port to the TM0 mode emitted at the output port, as shown in Fig. 11(a). Similarly, the TM0 mode launched from the input port can also be converted to the TE0 mode or be kept as the TM0 mode, depending on the phase difference φ2, as shown in Fig. 11(b).

The launched mode can be further converted to the circularly polarized light beam by adjusting the phase difference φ2. When φ2=π/2, the launched TE0 mode can be converted equally to the TE0 and TM0 modes with the same powers by the polarization converter. Then the phase difference δ between the TE0 and TM0 modes can be set as 2m±0.5π by tuning the heating power of PS #3 elaborately. As a result, the mode field pattern observed by the camera did not change, as the polarizer is rotated without a QWP [see the upper portion of Fig. 11(c)]. When a QWP is further inserted between the lens and the polarizer, the circularly polarized light is converted to the linearly polarized light, and thus the SOP can be characterized easily and clearly by the polarizer, as shown at the bottom of Fig. 11(c). The maximum transmittance is achieved when the axis of the polarizer is rotated to 45° or 195°, and the minimum transmittance is achieved when the axis of the polarizer is rotated to 135° or 315°.

To further demonstrate the generation of the arbitrary SOP by using the present PC, a polarimeter (PAX1000IR2) working at the 1550 nm wavelength band was used to characterize the SOP of the light beam generated at the output port. Figures 12(a) and 12(b) show the recorded SOP plotted on the Poincaré sphere for the launched TE0 and TM0 modes. Here the SOP is described with normalized Stokes parameters, i.e., S1,S2, and S3. For the input TE0 mode, as shown in Fig. 12(a), PS #2 was tuned with different powers to make the PER vary from −∞ to ∞. Meanwhile, for any given power P2 applied to PS #2, the power P3 applied to PS #3 was scanned from 0 to 25 mW with a step of ∼0.4mW, so that the phase difference between the TE0 and TM0 modes is swept from 0 to 2π. The power P3 sweeping traces the parallel circular orbits on the Poincaré sphere, while the step size of the power P2 defines the spacing between adjacent orbits. The measured results have a good correspondence with the simulation result shown in Fig. 2. Theoretically, when P2=0, the TE0 mode with a high PER is generated, it corresponds to the point [S1,S2,S3]=[−1,0,0] on the Poincaré sphere, while the SOP is kept unchanged when scanning the power P3. Note that the SOP of the emitted light changes in some degree due to the propagation in the output fiber; moreover, the heating-induced thermal cross talk also breaks the SOP to a certain extent. As a result, the measured SOP traced a small circular orbit, as shown in Fig. 12(a), and the swept point [S1,S2,S3]=[−0.99,−0.13,−0.04] has the maximal negative PER of ∼−23dB, indicating a TE0 mode with high PER is generated. Meanwhile, at the far side of the Poincaré sphere, point [S1,S2,S3]=[1,0.05,0] achieves the maximal positive PER of ∼32dB for the case of P2=19mW, indicating a complete conversion from the TE0 mode to the TM0 mode. Similar phenomena are observed for the case with the input TM0 mode, as shown in Fig. 12(b). Two nearly perfect points [S1,S2,S3]=[−1,0,−0.02] (with PER=−34dB), [S1,S2,S3]=[1,−0.03,−0.03] (with PER=33dB, at the far side of the Poincaré sphere) are achieved. In general, the record PER tuning range is 55 and 67 dB for the launched TE0 and TM0 modes, respectively.

For the present structure, any SOP can be generated easily from the input TE0 or TM0 modes by controlling the phase shifting of PS #2 and PS #3. In contrast, when an elliptically polarized light beam is input, the phase shifting of PS #1 should also be adjusted carefully to make sure the phase difference δ=2π±0.5π, and hence one can traverse the entire Poincaré sphere. For example, the input light is set to be ∼45° linearly polarized, and the feeding powers of PS #1, PS #2, and PS #3 are simultaneously swept from 0 to 40 mW with 18 steps. The ∼6000 points recorded by the polarimeter can fully cover the entire surface of Poincaré sphere benefiting from the device’s larger PER range, as shown in Fig. 12(c), proving that one can convert two arbitrary SOPs with the proposed PC. The proposed PC is intrinsically narrow in bandwidth due to the high birefringence of silicon photonic waveguides [30]. Here a large PER range can be achieved in a wide bandwidth by appropriately applying the control power to the PC optimized for different wavelengths. Figure 12(d) shows the measured PER range for the launched TE0 mode when operating with different wavelengths. Here the powers P2 and P3 are swept to produce ∼1000 points on the Poincaré sphere, and the points with the maximized PER are recorded in Fig. 12(d), showing that the PC has a high PER range of 54–85 dB in the wavelength range of 1530–1620 nm.

Table 1 shows the summary of the representative PCs reported. Currently, there are mainly two routes for the realization of on-chip polarization management. One is using the combination of PSRs and a 2×2MZI [25–27], while the other is using the combination of polarization rotators and phase shifters [30]. Theoretically, to achieve arbitrary SOP conversion, one has to introduce two PSRs, three MZIs, and two MMIs. However, the imperfection performances of the PSRs and the MMIs mean it has a limited PER range of less than 23 dB; thus, it is difficult to traverse the Poincaré sphere as demonstrated in Ref. [27]. Usually, the multistage design has to be introduced to increase the PER as desired [25,27]. Although a PER of 41 dB can be achieved, the total length is larger than 4.5 cm, and the devices’ behavioral predictability also decreases prominently. In comparison, our scheme contains a polarization converter and two PSs and has an ultracompact layout footprint. The critical PDMC works on the principle of mode hybridity and mode evolution of an adiabatically tapered ridge waveguide [42,44]. Meanwhile, the DMPS based on a tapered trident waveguide also works adiabatically [45]. As is well known, adiabatic tapers usually work with a broad bandwidth and large fabrication tolerances. Moreover, the structure symmetry of the DMPS is helpful to ensure the power-splitting ratio of 50%:50% for both TE0 and TE1 modes, as desired. Therefore, our scheme has an ultracompact and robust framework, featuring comprehensive advantages in the device footprint, the PER, the bandwidth, and the EL. As a result, our scheme has an ultracompact, robust framework, and features comprehensive advantages in footprint, PER, bandwidth, and EL.Table 1.

Performance Metrics Comparison of the Representative PCs

In conclusion, we have proposed and demonstrated a novel PC by forming two phase shifters on a high-performance polarization converter’s input/output waveguide. For the input light beam with arbitrary SOP, its Ex and Ey components excite the TE0 and TM0 modes, respectively. The PS #1 and polarization converter reallocate the PER of the TE0 and TM0 modes, while PS #3 tunes their phase difference. Thus, one can achieve the conversion of two arbitrary SOPs. The proposed PC works on the adiabatic mode evolution principle and is the structure of perfect symmetry, thus having larger fabrication tolerance. As a result, our scheme is ultracompact and robust and shows comprehensive advantages in footprint, PER, and EL. The fabricated PC has a compact layout footprint of ∼150μm×700μm, an EL of less than 1 dB, and a record PER range of >54dB in the wavelength range of 1530–1620 nm. One can convert two arbitrary SOPs with the proposed PC by feeding the PSs #1–3 with suitable power. Such a compact, high-performance polarization management device could be vital in many applications.