In order to overcome the on-orbit single-event flip and realize flexible and reliable multiple working modes, a refresh imaging system based on Xilinx field programmable logic devices and refresh chip of Fudan Microelectronics group company limited is designed. Using a single set of daisy chain structure serial bus to control the serial port of 5 sets of refresh imaging unit, FPGA internally converts the received data and then configures or refills the refresh chip. The refresh enable signal is used to control whether the refresh chip is powered on, and at the same time decides whether the FPGA is loaded from PROM in the master and parallel mode or loaded under the control of the refresh chip in the parallel mode. Through the control level setting, the selection of the loading data source is realized. After each power supply is completed, the external reset signal is used to refresh the chip reset, meets the timing requirements of refreshing the chip to start configuration immediately after reset. The experimental results show that the transmission time of a single packet of 204 byte data is only 0.377 6 ms with the baud rate of 625 kbit/s in daisy chain mode, which is much lower than the 2.01 ms required to refresh the serial port, and multiple groups of time-sharing work can be performed. The refresh imaging system using a small number of single-ended control signals combined with a daisy chain serial bus has a variety of working modes that are stable and reliable, with design flexibility and on-track maintainability.