Microelectronics, Volume. 53, Issue 5, 841(2023)

Design of a Buffer Optimization Architecture for ZynqNet Hardware Accelerator

CHEN Zhuo1, CHEN Yiduo1, TIAN Chunsheng2, QIU Peiyi3, and DI Zhixiong1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    Convolutional neural network ZynqNet is widely used in edge devices. However, the existing FPGA hardware acceleration schemes are not able to meet the real-time requirements of high-demand scenarios, as their frame rates are limited to less than 30 FPS. This paper focuses on the improvement of ZynqNet's FPGA acceleration performance by designing a parallel computing structure based on multiple feature blocks, optimizing support for Expand layer to enhance feature reuse, and optimizing output cache to reduce the number of memory accesses efficiently. Furthermore, A depth-first feature and weight cache mechanism is proposed, utilizing a multi-bank cache mode to enable one-cycle feature and weight reading. Based on the Xilinx Xc7z045 FPGA chip, the accelerator hardware implementation and performance test are completed, the operating frequency is 166 MHz, and the computing performance can reach 49 FPS. Compared to the traditional scheme of deploying the entire network to FPGA, the proposed approach delivers three times the acceleration and five times the improvement in energy efficiency ratio.


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    CHEN Zhuo, CHEN Yiduo, TIAN Chunsheng, QIU Peiyi, DI Zhixiong. Design of a Buffer Optimization Architecture for ZynqNet Hardware Accelerator[J]. Microelectronics, 2023, 53(5): 841

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    Paper Information


    Received: Mar. 4, 2023

    Accepted: --

    Published Online: Jan. 3, 2024

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