Aiming at the high-speed data readout from the on-chip memory of the uncooled infrared detector,a low-latency sensitive amplifier for the on-chip memory of the uncooled infrared detector is designed.As the pixel array of uncooled infrared detectors continues to increase,the requirements for the on-chip memory of uncooled infrared detectors are also higher,and a higher-speed memory is needed for the internal data storage of the infrared detector.Reducing the delay time of the sensitive amplifier is a reliable method to increase the data transmission speed.In this paper,the traditional cross-coupling structure of the sensitive amplifier is improved.Compared with the traditional cross-coupling structure of the sensitive amplifier,a completely complementary second-stage cross amplifying circuit is added,and an intermediate stage composed of NMOS is used to couple the two-stage operational amplifier.The improved new sensitive amplifier can quickly and effectively amplify the voltage difference on the bit line,and at the same time improve the problem of low sensitivity.The sensitive amplifier designed in this paper uses TSMC 65 nm process.Under the conditions of 5 V working voltage and 100 mV bit line voltage difference,the simulation results show that the data readout delay is only 25.19 ps.Compared with the cross-coupled sensitive amplifier,the readout delay is reduced by 37.07%.At the sametime,under the simulation conditions of the full process angle,the ambient temperature is －45 ℃to 125 ℃,the delay simulation maximum value of the new sensitive amplifier is only 39 ps,and the minimum value is 17.1 ps.