AlGaN/GaN high-electron-mobility transistors (HEMTs) have demonstrated state-of-the-art performance for high frequency and high-power applications.^[1–4] The strong polarization effect in conventional AlGaN/GaN HEMTs results in normally-on devices, while normally-off operation is preferred to in practical circuits in terms of maintaining the system safety, reducing power consumption, and simplifying circuit design.^[5,6] Recess-gate metal–oxide–semiconductor HEMTs (MOS-HEMTs) have been widely studied to achieve normally-off GaN-based devices, which have smaller leakage current and larger gate voltage swing compared with Schottky-gate HEMTs.^[7,8] However, there exist a large amount of interface charges between gate dielectric and nitride semiconductor, being one of the critical issues that restrict the development of device performance and reliability.^[9,10] For recess-gate devices, the plasma etch process of gate trench may cause rough nitride surface, leading to worse interface quality of MOS-HEMTs.^[11–13] Therefore, the interface analysis as well as its improvement is of vital importance for GaN-based recess-gate MOS-HEMTs.

Generally, there exist three kinds of oxide-related charges in GaN-based MOS-HEMTs having major influence on device performance and reliability, including interface traps, interface fixed charges, and border traps.^[14,15] The previous works about normally-on MOS-HEMTs demonstrated that interface traps caused transient threshold voltage (V_th) instability while border traps induced retentive V_th shift.^[16] The high density of interface fixed charges does not exhibit trapping effect, but it will lead to a negative V_th shift, being an obstacle to normally-off operation. Various methods have been developed to solve the interface issue, which can be classified into two types either by effective removing the native oxide layer^[17] or by forming a high-quality interfacial layer.^[18] In our previous work, we presented diffusion-controlled interface oxidation (DCIO) process,^[19,20] which resulted in an increase in the conduction band offset at Al₂O₃/AlGaN interface by over 0.6 eV and a decrease in MOS interface charges by about 4 × 10¹² cm⁻² DCIO is a promising interfacial engineering method for both MOS-HEMTs with and without recess gate. This novel interface oxidation method followed by wet etch was then used for the post-etch surface treatment of normally-off Al₂O₃/AlGaN/GaN MOS-HEMTs, leading to an improvement of channel transport property, on-resistance, and breakdown voltage.

To evaluate the interface treatment method comprehensively, quantitative characterization of interface charges in detail is desirable. The change of interface fixed charges can be easily derived from a voltage shift of transfer sweep or capacitance–voltage (C–V) curves. Many methods have also been reported to map the interface traps in GaN devices, such as frequency-dependent C–V measurement,^[21] conductance method,^[22–24] and transient current or capacitance.^[25,26] For the border traps, however, it is quite difficult to identify the trap density and its mapping because of the very long time constant during de-trapping process and uncertain trap location away from interface. In this paper, normally-off Al₂O₃/AlGaN/GaN MOS-HEMTs were achieved with fully recessed gate, and then the influence of DCIO treatment and wet etch after recess etch on trapping effect was investigated in detail. Sequential hysteresis C–V sweeps with increased gate swing voltage show two types of voltage shift induced by interface trapping and border trapping, respectively, which is similar to the case in normally-on devices. Photo-assisted C–V measurement^[27,28] was used to identify the activation energy and density distributions of deep-level interface traps and border traps. The major border traps have an activation energy of de-trapping process about 3.29 eV for both two devices with different post-etch surface treatment methods.

The AlGaN/GaN epilayers used in this paper were grown by metal organic chemical vapor deposition on sapphire substrate, consisting of a 180-nm AlN nuclear layer, a 0.8-μm carbon-doped GaN buffer layer, a 1-μm unintentionally doped (UID) GaN channel layer, a 0.6-nm thick AlN interlayer, a 21.6-nm Al_0.25Ga_0.75N barrier layer, and a 2.9-nm GaN cap layer from bottom to top, as shown in Fig. 1. Hall measurement shows that the carrier density and mobility are 9.78 × 10¹² cm⁻² and 1675 cm²/V ⋅ s, respectively.

Device fabrication started with Ohmic contacts of Ti/Al/Ni/Au. Ohmic contact resistance of 0.52 Ω ⋅ mm was achieved after rapid thermal annealing at 880 °C in N₂ for 50 s. Then mesa isolation was performed by inductively coupled plasma (ICP) etch with a depth of 125 nm, followed by 100-nm SiN passivation layer grown with plasma-enhanced chemical vapor deposition (PECVD). Before gate fabrication process the PECVD-grown SiN layer and Al_0.25Ga_0.75N barrier layer beneath gate area were completely removed using CF₄ and BCl₃/Cl₂ plasma etch in sequence. After plasma etch, the surface contaminant and residual photoresist were cleaned by organic solutions and NH₃ ⋅ H₂O (1:6) at 55 °C. To improve the post-etch surface morphology, DCIO oxidation treatment^[19] and wet etch in 1:5 HCl solution were carried out. Then 20-nm Al₂O₃ gate insulator layer was grown by atomic layer deposition (ALD) at 300 °C, following in situ nitridation plasma pre-treatment. The gate electrodes of Ni/Au were evaporated on the Al₂O₃ gate insulator layer. Finally, the device underwent post metallization annealing (PMA) in O₂ at 450 °C for 5 minutes using rapid thermal annealing system.

Two kinds of devices with different post-etch surface treatment processes were studied, the one with the aforementioned process (sample 1#) and the controlled one without DCIO oxidation and wet etch (sample 2#). MOS-HEMTs have T-shaped gate with gate foot length (L_G) of 1 μm, gate cap length of 2.8 μm, and gate width (W_G) of 50 μm. The gate–source (L_GS) and gate-drain (L_GD) distance are 2.5 μm and 6.5 μm, respectively. Ring diode were also fabricated for C–V measurement, with gate diameter of 130 μm and gate-ohmic distance of 25 μm.

The interface quality of recess-gate normally-off MOS-HEMTs was characterized using transmission electron microscope (TEM) as shown in Fig. 2. There exists about 5 nm over etch into the GaN channel layer for the gate trench process. Enlarged views at Al₂O₃/GaN interface show that a rough interface can be observed for the controlled sample, which will cause a high density of interface charges and degrades the channel transport property of recess-gate normally-off MOS-HEMTs. MOS-HEMTs with DCIO oxidation and wet etch post-etch surface treatment show a sharp Al₂O₃/AlGaN interface by effective removal of surface damage and native oxide.

Figure 3(a) shows the transfer characteristics of normally-off MOS-HEMTs with different post-etch surface treatment processes, where the drain voltage (V_D) is 10 V and the gate voltage (V_GS) sweeps from 0 V to 15 V. V_th is defined as the maximum gate voltage where the drain current is below 10 μA/mm, estimated to be 2.8 V and 3.1 V for samples 1# and 2#, respectively. DCIO treatment and wet etch after recess etch lead to an increase in maximum drain current (I_d) from 174 mA/mm to 294 mA/mm and an increase in peak transconductance (G_m) from 14 mS/mm to 40 mS/mm. In addition, the OFF-state leakage current reaches 1 mA/mm at V_D = 94 V for sample 2#, while the breakdown voltage increases up to 260 V for sample 1# with DCIO treatment and wet etch, as shown in Fig. 3(b).

It is obvious that post-etch surface treatment with DCIO treatment and wet etch results in improved device performance. The interface issue of recess-gate Al₂O₃/AlGaN/GaN MOS-HEMTs was studied using C–V hysteresis measurement as shown in Fig. 4. During each hysteresis sweep, gate voltage is swept from the maximum gate voltage to 0 V and then swept back. The maximum gate voltage during each sweep is defined as program voltage (V_p), which is increased from 6 V to 15 V with step of 1 V. The ascending region in C–V curve corresponds to the accumulation of electron at Al₂O₃/GaN interface, and capacitance plateau represents the capacitance of Al₂O₃ dielectric (C_Al2O3). Devices with DCIO treatment and wet etch method leads to a higher saturation capacitance and a negative V_th shift.^[21] The V_th shift and C–V hysteresis caused by defective charges can be distinctly viewed. The voltage hysteresis is defined as ΔV₁ for each sweep, which is caused by the trapping effect of interface traps. ΔV₂ represents the entire positive shift of backward sweep C–V curves with an increase in V_p compared to the initial V_p of 6 V. This voltage shift induced by border trapping is cumulative because of the very large de-trapping time constant.^[16]

Figure 5 shows the voltage shift extracted for C–V hysteresis sweeps with program voltage ranging from 6 V to 15 V. The trap density can be calculated by the following equation:

$$ \begin{eqnarray}{N}_{{\rm{T}}}=\displaystyle \frac{{C}_{{\rm{OX}}}\Delta V}{q},\end{eqnarray}$$ (1)

To activate the de-trapping of border traps with very large time constant, photo-assisted C–V measurement was carried out. Figure 6 shows the C–V characteristics of normally-off MOS-HEMTs before and after light illumination. The reference C–V curve (black curve) is firstly given under dark condition. With gate voltage swept from 0 V to 8 V, the electrons will be captured by border traps. Then the second sweep under dark condition gives C–V curves (gray curves) after filling of border traps. For photo-assisted C–V measurement, the devices are illuminated by monochromatic light for 60 s to enhance the electron emission from border traps, following which the C–V curve is swept from 0 V to 8 V immediately under dark condition. The photo-assisted C–V sweeps are repeated with wavelength of monochromatic light decreasing from 500 nm to 360 nm.

After light illumination with wavelength shorter than 400 nm, there is a significant negative voltage shift of C–V curves due to the de-trapping of border traps. With a decrease in wavelength, the higher photon energy causes a larger negative voltage shift. For sample 2# without DCIO treatment and wet etch, the voltage shift caused by photo-assisted de-trapping process increases from 0.06 V to 0.54 V with the wavelength decreases from 500 nm to 375 nm as shown in Fig. 6(a). For sample 1#, the voltage shift shows an increase from 0.05 V to 0.35 V. The photon energy (E), i.e., activation energy of border traps (E_A), can be calculated using E = hν where h is the Boltzmann’s constant and ν is frequency of photon. With the activation energy ranging from 2.48 eV to 3.29 eV, the density of border traps contributing to voltage shift is 1.11 × 10¹² cm⁻² and 7.94 × 10¹¹ cm⁻² for samples 2# and 1#, respectively. Then, the C–V curves are further recorded under the wavelength of incident light varying from 400 nm to 360 nm with a step of 5 nm. As shown in Fig. 6(b), the most remarkable voltage shift appears at 375 nm of light illumination. This indicates that the major border traps have an activation energy about 3.29 eV.

To obtain the trap distribution as activation energy, the state density of border traps with activation energy of E_A can be estimated by using the following equation:^[29]

$$ \begin{eqnarray}{D}_{{\rm{T}}}(E={E}_{{\rm{A}}})=\displaystyle \frac{C\cdot \Delta V}{q\cdot \Delta h\nu },\end{eqnarray}$$ (2)

In conclusion, interface issue of normally-off recess-gate Al₂O₃/AlGaN/GaN MOS-HEMTs with different post-etch surface treatment was investigated using hysteresis C–V and photo-assisted C–V method. DCIO and wet etch process results in a decrease in interface and border traps by 27% and 14%, respectively, leading to the improved device performance. Photo-assisted C–V reveals that both samples with different post-etch surface treatment have the similar distribution of border traps, showing peak state density at activation energy of 3.29 eV. The peak border trap density for sample with DCIO and wet etch is 2.60 × 10¹² cm⁻² ⋅ eV⁻¹, reduced by half compared with the controlled sample.