Memristors have emerged as key devices in neuromorphic computing due to their high parallel computing efficiency and low power consumption characteristics. However, array scale expansion is often constrained by traditional electrical interconnection bandwidth bottlenecks and signal attenuation effects. To address these limitations, we propose an integrated architecture for memristor arrays based on optical network-on-chip, utilizing photonic interconnections to overcome physical scaling constraints. We develope a topological packaging structure for memristor arrays and validate its sensitivity to task accuracy through analysis, demonstrating stable computational performance of memristor IP cores under complex conditions. To address the issue of cumulative computation delay within memristor arrays, we present a space-task collaborative optimization mapping algorithm for IP cores. This algorithm minimizes path transmission hops by reconstructing subtask mapping layouts. Additionally, to resolve the problem of multi-task path crosstalk in optical interconnection networks, we design a task-aware low-crosstalk mapping algorithm. This algorithm establishes a collaborative optimization model between photonic device physical characteristics and task communication graphs, reducing interference risks in non-blocking transmission. Experimental results demonstrate that this approach effectively enhances the scalability and computational reliability of large-scale memristor arrays, providing a theoretical framework and technical paradigm for optoelectronic co-design of high-density neuromorphic chips.