A fine step frequency synthesis method based on double loop system is proposed to solve the integer sideband spur problem of fractional frequency division phase lock. According to the working principle of variable reference to suppress fractional frequency integer sideband spurs, a fine step frequency synthesis system is formed by cascading a first order integer frequency division phase locked loop(PLL) and a first order fractional frequency division PLL. The N frequency division and M parameters of the integer PLL are adjusted through software algorithms, and finally the full frequency band spurs index is optimized. A broadband (bandwidth：4 8 GHz) fine step (1 kHz) frequency synthesizer is designed according to the proposed method. The measured spurs is better than 75 dBc, phase noise is better than -96 dBc/Hz at 1 kHz, and frequency hopping time is less than 47 μs.