GaN-based electronic materials are considered as excellent candidates for power switching applications, owning to their outstanding properties such as high electrical breakdown field and high saturated electron mobility.^[1,2] As for AlGaN/GaN metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT), silicon nitride (SiN_x) dielectric deposited by low pressure chemical deposition (LPCVD) technique offers the absence of the Ga–O bonds and a large conduction band offset (ΔE_c = 2.3 eV), yielding an effectively suppressed gate leakage and a large gate swing.^[3–5] In addition, the free plasma-induced damage and high deposition temperature (780 °C) provide a high quality dielectric film with low defect density,^[6] thus offering excellent thermal stability and large forward breakdown electric field (14 MV/cm).^[7] However, long term stability and reliability for GaN MIS-HEMT with LPCVD SiN_x gate dielectric still need extensive evaluation before commercial deployment.

The GaN MIS-HEMT is often adopted in cascode configuration, requiring a negative gate bias to deplete the two-dimensional electron gas (2DEG) channel and sustain the off-state high drain voltage.^[8,9] Marcon et al.^[10] have revealed that the off-state breakdown is time-dependent and even a small voltage stress can trigger hard breakdown after a sufficient time stress. Furthermore, the effects of ultraviolet light and substrate bias on the time-dependent breakdown (TDB) were also evaluated previously.^[11,12] Generally, the absolute value of negative gate bias is relatively smaller than that of drain voltage under off-state stress condition. However, both negative gate bias and drain voltage are accelerated factors which will inevitably bring defects inside the gate dielectric and GaN materials, and eventually cause catastrophic failure of devices.^[9,10] In the enhance-mode LPCVD-SiN_x/GaN MIS-FET, Hua et al.^[13] found that the threshold voltage stability shows an obvious dependence on the negative gate bias under reverse-bias step-stress. Until now, researchers have been mainly focusing on electron detrapping process in the gate dielectric induced by moderate negative gate stress with the overdrive voltage (V_GS – V_Th) smaller than −80 V.^[14] The negative gate stress condition can be regarded as special off-state stress with a certain large drain to gate voltage (V_DG) bias, which is also able to cause breakdown of gate dielectric or GaN materials. However, there are no reports on comparing time-dependent breakdown between off-state stress and negative bias stress, which is obviously beneficial for further understanding the inherent physical mechanism.

In this paper, rapid breakdown of GaN MIS-HEMT with LPCVD SiN_x gate dielectric under negative gate bias stress (V_GS < 0 V, V_DS = 0 V) and off-state stress (V_G < V_Th, V_DS > 0) is investigated by using static constant voltage stress (CVS) tests. The substrate and source in both stress cases are grounded (V_S = V_Sub = 0). The purpose of setting the two type stress conditions is to analyze the influence of V_GS and V_DS on breakdown process under a fixed drain to gate voltage (V_DG) separately. Simulation method is utilized to further analyze the underlying degradation mechanism of the two type stress conditions. After rapid breakdown tests mentioned above, a large drain to gate voltage stress (in this paper, V_DG = 200 V) sufficient to generate large numbers of defects but not enough to cause rapid breakdown of device is selected to monitor the long-term evolution of electric parameters, which is beneficial for further underlying the inherent mechanism of the two stress conditions.

The devices used in this paper are manufactured on the standard CMOS production line. The metal–organic chemical vapor deposition (MOCVD) GaN epitaxial layer was grown on a 6-inch (111) Si substrate (1 inch = 2.54 cm), from bottom to top is a 4-μm GaN buffer, a 300-nm/25-nm AlGaN/GaN heterojunction and a 2-nm GaN cap. A 0.7-nm AlN interlayer is sandwiched between the AlGaN/GaN heterojunction. The device features a dimension of L_g/L_gs/L_gd/W_g at 3-μm/3.5-μm/3.5-μm/100-μm. A 35-nm SiN_x was deposited by LPCVD as the the gate dielectric as well as the first passivation layer. More process details are illustrated in our previous works.^[15]

Figure 1 shows the transfer and off-state breakdown characteristics of devices used in this work. The devices deliver excellent gate control ability with a small subthreshold swing of 87 mV/decade and a high on/off current ratio of 10⁹. The threshold voltage (V_Th) is approximately −10 V, which is defined at drain current of 10 μA/mm with drain voltage (V_DS) of 1 V. The hysteresis of V_Th is small at the maximum sweep gate voltage (V_GS) of 10 V. The drain to gate breakdown voltage (V_{DG_max}) is 360 V with V_G = V_Th − 5 V and V_S = V_Sub = 0. It worth noting that the drain current is mainly determined by the gate leakage current.

The selection of drain to gate breakdown voltage (V_DG) is around 80% of V_{DG_max}, and seven devices per group of breakdown voltage are adopted. The TDB during negative bias stress is shown in Fig. 2(a), time to breakdown (t_BD) is defined at the point when I_GS exceeds 10⁻² mA/mm, lifetime extrapolation of absolute V_GS for 20 years based on 1/E model^[7] with failure rate of 63.2% and 0.01% are 209 V and 162 V, respectively (Fig. 2(b)). Therefore, SiN_x dielectric deposited by LPCVD delivering excellent long-term negative bias breakdown property. For off-state stress condition with a fixed drain to source voltage (V_DG = 295 V, same as the negative bias stress), t_BD is approximately 1 order of magnitude shorter for V_DS = 280 V than that of V_DS = 270 V (Fig. 3), which is mainly account of the more sever ionizing collision of hot electron effect in gate to drain access region.^[16] Furthermore, the comparison between negative gate voltage stress (V_GS = −295 V, V_DS = 0 V) and off-state stress (V_GS = −15 V, V_DS = 280 V) on time-dependent breakdown indicates that the mean t_BD is just 0.5 order of magnitude shorter for off-state stress (Fig. 4(a)). The possible reason of this phenomenon is ascribed to that the external voltage under both bias conditions is sustained by the dielectric and depletion region in GaN layers between gate and drain electrodes. Besides, unlike the forward bias time-dependent breakdown process,^[7,17–20] two sudden increasing trend in I_GS occurs during both off-state and negative bias stress conditions (Fig. 4(b)). The lower I_GS for off-state stress (Fig. 4(a)) reflects the difference of leakage paths between the two stress conditions, the inherent mechanism will be discussed in Subsection 3.2. We previously confirm that the forward breakdown voltage of GaN MIS-HEMT with LPCVD SiN_x dielectric used in this paper is 45 V. When the maximum of electric field applied in the dielectric exceeds 11.4 MV/cm, the breakdown will be triggered in dielectric first. Then, most of the voltage is sustained by the GaN epitaxial layer and causes the second breakdown.

The t_BD of MIS-HEMT for the two stress conditions both follow a Weibull failure distribution, which can be described as

$$ \begin{eqnarray}F({\rm{t}})=1-\exp \left[-\left(\displaystyle \frac{t-\gamma }{\eta }\right)\right],\end{eqnarray}$$ (1)

$$ \begin{eqnarray}\mathrm{ln}[-\mathrm{ln}(1-F(t))]=\beta \mathrm{ln}(t)-\beta \mathrm{ln}(\eta )\end{eqnarray}$$ (2)

$$ \begin{eqnarray}\beta =m\times N,\end{eqnarray}$$ (3)

Simulations for rapid breakdown conditions (@V_DG = 295 V) verify that negative bias stress will induce significant peak electric field under both edges of gate–drain edge and gate–source, and the peak electric field for gate–source is slightly higher than that of gate–drain even for the device with L_gs = L_gd (Figs. 6(a) and 6(c)), which implies that the formation of per-location paths is most likely to occur under the edge of gate–source. While peak electric field for off-state stress is mainly localized at the edge of gate–drain (Figs. 6(b) and 6(c)). In the whole, the peak electric field of both edges of gate–drain edge and gate–source for negative bias stress are higher than that of the edge of gate–drain for off-state stress (Fig. 6(c)).

For further underlying the time-dependent breakdown mechanism of negative bias and off-state stress for GaN MIS-HEMT with LPCVD SiN_x dielectric, a large drain to gate voltage stress (in this paper, V_DG = 200 V is adopted) sufficient to generate large numbers of defects but not enough to cause rapid breakdown of device is selected to monitor the long-term evolution of electric parameters.

During negative bias stress (V_GS = −200 V, V_DS = 0 V, @V_DG = 200 V as shown in Fig. 7(a)) process, the threshold voltage shift to the positive (ΔV_Th = 2.45 V after stressed for 10000 s), and on-resistance (R_on) continues to increase (Fig. 7(b)) in the whole time stress window. Under negative bias, the injection of electron from gate will be trapped by the pre-existing defects in SiN_x dielectric, AlGaN barrier and buffer layers.^[14,22] Those electrons will deplete the 2DEG channel and shift the threshold voltage positively. Moreover, the leakage monitoring (Fig. 8(a)) shows that from 100 s to 10000 s, the leakage of gate (I_GS) and drain to gate (I_DG) increase about 0.3 and 0.5 order of magnitude gradually. Strikingly, the leakage of source to gate (I_SG) increases about 1.0 order of magnitude and exceeds I_DG gradually, which further indicates that despite the existence of two peak electric under the gate edges of source and drain for the MIS-HEMT with L_gs = L_gd, breakdown for negative bias stress occurs mainly concentrated below the edge of gate–source. After adequate recovery process (after the static storage of 10⁶ s and then illuminated under ultraviolet light for 10⁴ s), significant negative shift of V_th (ΔV_Th = −2.2 V as shown in Figs. 7(c) and 10(a)) and about 0.5 order of magnitude (Fig. 8(a)) increasing of I_GS underlying that the newly generated defects occurs in the SiN_x and SiN_x/AlGaN interfaces. Besides, the negligible degradation of on-resistance (R_on) after adequate recovery process (Fig. 7(f)) reflects the fact that the newly generation of defects are mainly located at the gate edges of source and drain. Therefore, combined with simulation results as Figs. 6(b) and 6(c), the formation of per-location paths will be first formed in SiN_x dielectric and then in AlGaN barrier below the edge of gate–source (as shown in Figs. 9(a)–9(c)).

While the negative shift of V_th (ΔV_Th = −2.35 V after stressed for 10⁴ s as shown in Fig. 7(a)) for off-state stress (V_GS = −15 V, V_DS = 185 V, @V_DG = 200 V) is mainly on account of the gradually generation of new defects of dielectric, more inherent mechanisms are related to gate to source leakage (I_GS) as shown in Fig. 8(b), the correlation analysis will be given below. The continued increase of R_on (Fig. 7(b)) during time stress reflects the trapping process in gate to drain access region. Similarly to negative bias stress, after adequate recovery process, the exhibited negative shift of V_th (ΔV_Th = −1.85 V for off-state stress as shown in Figs. 7(f) and 10(b)) and about 0.5 orders of magnitude (Fig. 10(b)) increasing of I_GS underlying that new defects were initially generated in the SiN_x dielectric. In addition, the negligible change of on-resistance (R_on) after adequate recovery process (Fig. 7(f)) reflects the fact that the newly generations of defects are mainly located under the edge of gate to drain (as shown in Figs. 9(e)–9(g)).

During off-state stress period of 10⁴ s (Fig. 8(b)), the drain leakage current is dominated by drain to substrate current (I_Sub), while the change of I_Sub during the whole stress period is negligible. When the stress time exceeds 2500 seconds, I_DG gradually decreases during each stress period from beginning to the end, which is attributed to electrons trapped by the localized defects inhibiting the trapping process. Then I_GS recovers to the initial value at the beginning of next stress period by the reason of electron–electron de-trapping. Moreover, I_GS is smaller than the previous one after each stress period, which is apparently account of the newly generated defects in SiN_x dielectric capturing more electrons and further inhibiting the trapping process.

In conclusion, the evaluations of stress voltage on the time-dependent breakdown characteristics for GaN MIS-HEMT with LPCVD SiN_x gate dielectric are investigated by combining experiment and simulation. SiN_x dielectric deliveres excellent long-term negative bias breakdown property. The lifetime extrapolation for 20 years based on 1/E model with failure rate of 63.2% and 0.01% are 209 V and 162 V, respectively. Furthermore, the time-dependent breakdown was investigated under both negative gate bias and off-state stress. For negative bias stress, the breakdown time distribution (β) decreases with the increase of negative gate voltage, because more electrons will inject into the dielectric and introduce more defects under a higher bias, thus fewer formed defects are needed for the per-location paths for higher negative gate bias stress. While β is larger at higher drain voltage for off-state stress, which means that higher V_DS will bring more electrons from 2DEG channel into the GaN layers, resulting in an increasing defects generation rate and larger β value. Two humps in the time-dependent gate leakage occurred during both breakdown conditions, which can be ascribed to the different newly generated leakage paths at different locations. Combining experiment and simulation results, the catastrophic breakdown of SiN_x dielectric will be triggered first, and then the GaN layer breakdown will occur subsequently. The peak electric field under the gate edges of source and drain is confirmed as main locations for the breakdown of negative gate voltage stress and off-state stress, respectively.