Microprocessors, Volume. , Issue 3, 24(2025)

A High-Speed Comparator Design with Rail-To-Rail Input

HAN Mei and ZHAO Hongjian
Author Affiliations
  • The 47th Institute of China Electronics Technology Group Corporation ,Shengyang 110000, China
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    Aiming at the slow speed of traditional comparators, a high-speed comparator with optional speed is proposed. The comparator applies a rail to rail input structure. The pre-amplification circuit of the high-speed comparator is composed of a two-stage differential amplifier, and the result of the amplifier is fed into a latch circuit to get the comparison result. The latch circuit reduces the comparator delay and increases the comparator speed . In the comparator circuit, a comparator reverse input mode selection circuit, a comparator speed mode selection circuit, a comparator output stage selection circuit, and a comparator lag terminal selection circuit are added. The reverse input of the comparator has eight selection modes, the speed of the comparator has four selection modes, and the lag end of the comparator has four selection modes. The rail-to-rail input structure of the comparator circuit can detect differential mode voltage of 2mV. A multifunctional comparator with rail to rail, optional speed and optional hysteresis end is realized.

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    HAN Mei, ZHAO Hongjian. A High-Speed Comparator Design with Rail-To-Rail Input[J]. Microprocessors, 2025, (3): 24

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    Paper Information

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    Received: Sep. 25, 2024

    Accepted: Aug. 25, 2025

    Published Online: Aug. 25, 2025

    The Author Email:

    DOI:10.3969/j.issn.1002-2279.2025.03.004

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