In synchronous digital hierarchy(SDH) , pointer adjustment during positioning will cause great jitter of output signal. In order to ensure the quality of signal, a de-synchronization circuit which is used in the receiving end of E1 tributary in SDH is proposed. The circuit contains an adaptive filter and a second-order digital phase-locked loop(PLL) with medium bandwidth. The numerical control oscillator in PLL consists of a serial accumulator and a dual-mode divider. It adopts the method of frequency discrimination and phase discrimination in parallel, and uses a digital filter. By establishing mathematical model, its working process and output jitter are analyzed. Simulation results show that the performance index meets the related standard of ITU-T.