Semiconductor Optoelectronics, Volume. 46, Issue 2, 318(2025)

Design of A High-precision Digital Delay System Based on Field-programmable Gate-array Internal Resources

FENG Wei1, YU Wenbo1, LUAN Chao2, XIANG Yuyan1, and LI Song1,3
Author Affiliations
  • 1College of Electronic Information, Wuhan University, Wuhan 430072, CHN
  • 2Beijing Institute of Control and Electronic Technology, Beijing 100045, CHN
  • 3Wuhan Institute of Quantum Technology, Wuhan 430206, CHN
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    To meet the demand for long-distance and high-precision delay in the echo simulation equipment of satellite-mounted laser altimetry systems, a digital pulse delay generator (DDG) architecture, based on the internal integration of special delay lines in field-programmable gate arrays (FPGAs), is proposed. A self-measurement compensation-type DDG consists of “interpolation delay line + three levels of coarse and fine time-delay circuits.” The CARRY4 interpolated delay line is leveraged to accurately measure the time difference between the arrival of the external trigger signal and the FPGA internal-clock-acquisition edge and thus locate the starting point of the time delay with high accuracy. Then, the three-level time delay scheme of coarse time counting is applied for sequential coarse and fine phase adjustments—this approach enables the realization of high-precision delay on long-time scales based on the starting moment of the trigger signal. The DDG design incorporates jitter self-measurement and calibration methods, which are applicable to both internal and external triggering. In addition, its design resources rely on FPGA on-chip-based resources, ensuring wide adaptability of the design. Experimental results show that when an oscillator with a frequency accuracy of ±0.5 ppm is used, a minimum-time-delay step of up to 37.5 ± 7.5 ps is obtained in the compensated externally triggered mode, and for a 2-ms delay, the output jitter is better than 270 ps (the root mean square error is 31 ps).

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    FENG Wei, YU Wenbo, LUAN Chao, XIANG Yuyan, LI Song. Design of A High-precision Digital Delay System Based on Field-programmable Gate-array Internal Resources[J]. Semiconductor Optoelectronics, 2025, 46(2): 318

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    Paper Information

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    Received: Dec. 30, 2024

    Accepted: Sep. 18, 2025

    Published Online: Sep. 18, 2025

    The Author Email:

    DOI:10.16818/j.issn1001-5868.20241230001

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