When the Global Navigation Satellite System (GNSS) receivers are applied to a portable handset, the power of the most power-hungry blocks, such as quadrature 2∶1 frequency divider, should be reduced. Therefore, this paper proposes a 1 V low power quadrature 2∶1 frequency divider at high speed and steady working in all process corners. First, the published high speed architectures are introduced. Then the static DC bias is calculated for the proposed architecture, and a small signal model for proposed flip-flop is developed and analyzed. Finally, a low power circuit is designed according to the analysis conditions of small signal model and the application requirements of GNSS receivers. Experimental results indicate that the proposed frequency divider works from 6.55 to 0.25 GHz, its consume current is only 0.8 mA, and the core area is 0.014 4 mm2. The proposed quadrature 2∶1 frequency divider is implemented in a 0.13 μm CMOS process, and can steadily work in a sub 1 V supply voltage. It has been successfully applied to low power portable GNSS receivers.