This Special Topic of the Journal of Semiconductors (JoS) features expanded versions of key articles presented at the 2023 IEEE International Conference on Integrated Circuits Technologies and Applications (ICTA), which was held in Hefei, Anhui, China, from October 27 to 29, 2023. IEEE ICTA is an IEEE flagship conference in the field of integrated circuits (IC) in China, which provides a communication platform for sharing the state-of-the-art techniques from experts in the field of ICs. Among the 93 papers presented at ICTA 2023, the Technical Program Committee and the Award Committee have selected 4 high-quality articles to recommend to the Special Topic of JoS, covering a wide range of technical fields, including one paper on RF ICs, two papers on Analog ICs and one paper on Wireline ICs.

The article in the field of RFIC is from University of Electronic Science and Technology of China^[1]. It introduces a frequency servo system-on-chip (FS-SoC) with a background output power calibration technique used in compact and ultra-low power cesium atomic clocks. By employing the power stabilization loop (PSL) technique, the FS-SoC ensures stabilized output power, thereby enhancing the accuracy of the atomic clocks. Fabricated using 65 nm complementary metal oxide semiconductor (CMOS) process, the phase noise performance of −69.5 dBc/Hz @ 100 Hz offset and −83.9 dBc/Hz @ 1 kHz offset with 19.7 mW power consumption is measured on the proposed FS-SoC. Moreover, when integrated into a cesium (Cs) atomic clock, the FS-SoC coupled with PSL achieves an Allan deviation of 1.7 × 10⁻¹¹ with a 1-s averaging time.

The first article in the field of Analog ICs is from Xi’an Jiaotong University and Qingdao Hi-image Tech. Co. Ltd.^[2]. It features a 16-bit, 18-MSPS successive-approximation-register (SAR) analog-to-digital converter (ADC) with hybrid synchronous and asynchronous (HYSAS) timing control logic, utilizing an on-chip delay-locked loop (DLL). The HYSAS scheme provides a longer settling time of the capacitive digital-to-analog converter (CDAC) compared to synchronous and asynchronous SAR ADCs, which effectively addresses incomplete settling or ringing in the DAC voltage for the cases of either on-chip or off-chip reference voltage sources. The finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm is utilized for foreground calibration of the CDAC’s mismatch in an off-chip field programmable gate array (FPGA). Fabricated with 40-nm CMOS, the proposed ADC achieves 94.02 dB spurious-free dynamic range (SFDR) and 75.98 dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input at an 18-MSPS sampling rate.

The second article is from Sun Yat-Sen University^[3]. The article introduces an event-driven charge pump (CP) loop with dynamic strength control (DSC) to enhance transient response with low power consumption in an output-capacitorless low-dropout regulator (OCL-LDO). Fabricated in 65-nm CMOS technology, the proposed OCL-LDO demonstrates remarkable recovery within 30 ns under a 200 mA/10 ns loading change with 410 nA quiescent current (IQ), achieving a state-of-the-art impressive (FoM) of 0.1 fs.

The article in the field of Wireline ICs is from Xi’an Jiaotong University^[4]. The paper introduces a versatile 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver (TRx) fabricated in a 28-nm CMOS process. The voltage-mode driver with a 4-tap feed forward equalizer (FFE) is incorporated in the quarter-rate transmitter (TX). On the other hand, a continuous-time linear equalizer (CTLE), a 3-stage high-speed slicer, and a digital clock and data recovery (CDR) are employed in the half-rate receiver (RX). Additionally, a high-speed track-and-regenerate comparator is proposed to enhance settling time in the RX slicer. Through measured results, the TRx achieves a maximum data rate of 56 Gb/s with chip-onboard assembly. Power consumption is measured at 125 mW for the TX and 181.4 mW for the RX, both powered from a 0.9 V supply.

Finally, we would like to thank the authors for contributing their articles and meeting the tight deadlines required for this Special Topic. We also thank many anonymous reviewers whose feedback and comments ensure the high quality of the journal. We hope that this JoS Special Topic on ICTA 2023 will provide a useful cross section of the recent progress on the development of the ICs.