Based on a 4-stage cascade folding interpolation architecture, a 12-bit ADC was presented. The circuit was designed in a 0.18 μm SiGe BiCMOS process. The single core achieved a conversion speed of 1.5 GS/s, the output interface was 2-lane LVDS, and the latency was less than 7 ns. The front-end sample/hold circuit and folding interpolation quantizer adopted pure bipolar design, which could achieve 12 bit quantization accuracy without trimming. Finally, the design points and test results of the published layout were given.