A Σ-Δ fractional-N frequency synthesizer with broadband, low phase noise and low spurious was designed in a 65 nm CMOS process. Three voltage-controlled oscillators and a programmable frequency division link was adopted in the frequency synthesizer to achieve broadband output, and each voltage-controlled oscillator introduced an adaptive body-biasing technique to reduce the impact of PVT changes. A retiming unit was taken in the programmable frequency divider to synchronize the output, which improved the phase noise of the frequency divider. The automatic frequency calibration circuit adopted a structure that directly counted the voltage-controlled oscillator, which shortened the frequency lock time. A notch filter structure was added to the Σ-Δ modulator to reduce output quantization noise. The post simulation results showed that the frequency range of the quadrature signal that the frequency synthesizer could output was 0.2 ~ 6 GHz under 1.2 V power supply voltage. When the output frequency was 3.762 5 GHz, the phase noise was -113.59 dBc/Hz @1 MHz, the reference spurious was -59.3 dBc, and the power consumption was 91 mW.