Motivation. As artificial intelligence (AI) workloads escalate exponentially, ultra-thin, high-efficiency voltage regulator modules (VRMs) with exceptional power density become essential for backside-mounted configurations^[1]. Thus, high-density multiphase DC−DC converters are pivotal for implementing vertical power delivery (VPD) architectures in XPU platforms. Strategically positioning these converters beneath processors and maximizing spatial utilization enables core rail currents exceeding 2 kA while significantly reducing the power distribution network (PDN) losses compared to conventional solutions. The VPD configuration elevates system-level energy efficiency with >100 W power saving per processor, yielding megawatt-scale savings in a datacenter that uses ~100 000 processors. The synergy of 48 V power conversion architectures and advanced packaging techniques enables the industry’s commitment to balancing computational demands with CO₂ emission reduction and environmental sustainability.

Layout geometry. For a 1500 W XPU with 2 kA current at 0.75 V core supply voltage, 100+ or tens of DC−DC converters would be needed, even if one converter can provide 10−100 A. For conventional power delivery system with converters on the side(s), one or two centralized controllers with multiple power stages is a straight-forward solution. In a multidrop configuration shown in Fig. 2(a), one controller provides time-interleaved pulse-width modulation (PWM) signals to the power stages, while each power stage feeds a current sensing (CS) signal back to the controller. Meanwhile, sensing the instant V_OUT information over a large area on-chip or on-board imposes additional challenges. Therefore, it would be difficult for the multidrop configuration to scale up the number of converters and the output current capability.

To reduce the input current of the system in package, a third stage using integrated voltage regulators (IVRs) or fully-integrated voltage regulators (FIVRs) at positions C or D with voltage step-down DC−DC conversion is highly favorable. In such way, the number of balls of the package substrate and through-silicon vias (TSVs) of the silicon interposer can be saved from the power chain for the signal chain.

System architecture. A two-stage DC−DC power conversion from 48 V to sub-1 V is commonly employed in current industrial solutions^[2]. As shown in Fig. 1, an LLC resonant converter can serve well as an unregulated DC−DC transformer (DCX) for the lateral first stage at position A, to generate an intermediate bus voltage (IBV) with ultra-high power density and superior conversion efficiency, while an ultra-thin multiphase buck at position B should provide extremely fast load transient response as well as high efficiency and large voltage conversion ratio (VCR). With a larger VCR, the lateral current and thus the conduction losses on board would be greatly reduced.

On the other hand, for a back-side power delivery system, the converters are distributed in a ring shape (Fig. 2(b)) or as an array/net (Fig. 2(c)), making it complicated if using a centralized controller. Obviously, placing the converters in a ring shape or as an array provides uniformity to the power plane on board, in package, and/or on-chip^[3−6], improving the power integrity. And, a converter chip may consist of two or multiple interleaving phases^{[7, 8]}, making the system a multi-chip multi-phase solution^{[9, 10]}. Also, it brings good scalability for the number of converters and the output current capability.

In conclusion, AI power needs large-scale 2.5D/3D power conversion and delivery solutions, as a vertical power delivery architecture may save 100+ Watt power per processor. In a distributed multi-chip multiphase converter ring/chain or array/net, local feedback, current balancing, phase shedding and fault tolerance functions need a large number of extra I/O pins and routing resources, bringing new challenges to the power management IC design area. Moreover, hybrid converter topologies require extra efforts to tackle the above-mentioned new control issues in large-scale distributed converter ring/array. Scalability is the key.

In recent years, hybrid converters have been widely studied^[13]. They use switched-capacitor circuits to reduce the voltage stress of the power inductors and switches, and/or to reduce the inductor current, improving the power density and conversion efficiency. On ISSCC 2025, to have a theoretically fastest transient response of a hybrid buck topology, all power inductors should be energized immediately when a load transient is detected^{[10, 14]}. A fast−slow two-part dual-loop hybrid converter solution is proposed, with one loop using relatively large high-current inductors for high efficiency, and another high-frequency loop using a miniaturized inductor and low-voltage switches for fast transient response^[15].

Control strategy. There are several control strategies for such a large-scale power conversion: 1) multiple drop with a centralized controller, namely a master-slave scheme, 2) multiple drop converter ring in a daisy-chain configuration^{[3, 10]}, 3) a converter array with a global loop for current balancing while each converter has a local loop for fast transient response^[11], or 4) a converter array with each converter operates independently with no master^[12].

For these multi-chip multiphase DC−DC converter control schemes, besides the fundamental load transient speed consideration, there are a few more important new issues. First, current balancing between phases and chips is essential for good system reliability and high conversion efficiency. In a large-scale converter array, we would prefer a scheme that uses less I/O pin and routing resources for a current balancing net. Second, a phase shedding function that adaptively disables part of the phases/chips accordingly to the load condition, is favorable for achieving high efficiencies over a wide load current range^{[8, 10]}. A daisy-chain scheme may not be easily compatible with a phase shedding scheme, requiring smart solutions. Third, in a converter array, multiple distributed in-package V_OUT sensing points and feedback paths for the back-side local regulation loops would occupy a large number of I/O resources. Fourth, fault tolerance and reliability are important issues in a converter ring/array, as 100+ or tens of converters are used. Then, certain output power redundancy should be added to the converter ring/array.