The neutron scintillator detector is one of the main detectors for China Spallation Neutron Source (CSNS). High detection efficiency is the design goal of the second-generation neutron scintillator detector, which is in process of development, composed of neutron scintillation screen, wavelength transfer optical fiber and photoelectric converter. CSNS_VASD chip is an application-specific integrated circuit (ASIC) developed for China Spallation Neutron Source as the second-generation neutron scintillator detector.

This study aims to evaluate the performance of the front-end ASIC chip CSNS_VASD by experimental test.

The combined architecture of "ASIC test board plus digital readout board" was adopted for overall test system design. The ASIC test board was used to amplify, shape and distinguish signals whilst the digital readout board took the roles of configuring the ASIC and its auxiliary circuits, packing and caching the test data, and sending it to the back end for processing and analysis through optical fiber Ethernet. The relevant performance parameters of the chip were tested in the laboratory using exponential like wave test signal with amplitude of 10~120 MV, pulse width of 1 μs and frequency of 100 K as the input signal of ASIC chip, and the neutron beamline of CSNS.

The results show that the nonlinear error of CSNS_VASD is better than 1%, the equivalent voltage noise is better than 0.63 mV, the crosstalk value is better than 0.89%, and the detection efficiency of the detector is 40.7%@0.1 nm.

All of the test indexes meet the requirement of the design target. The successful development of the CSNS_VASD chip provides a reliable technical guarantee for the smooth construction of China Spallation Neutron Source.