Error correction is crucial for satellite-to-ground quantum key distribution (QKD). Among many error correction algorithms, polar codes have higher coding efficiency and error correction speed. In the satellite-to-ground QKD system based on polar codes, not only satellites face the problems such as volume, quality and power consumption, but also ground stations is constantly pursuing the integration of equipment. Therefore, in order to realize low-cost satellite-to-ground QKD equipment, a field programmable gate array (FPGA) based on successive cancellation (SC) decoder with low hardware complexity is proposed. The anaylsis shows that the decoder can achieve a throughput of 29.7 Mbit/s ^{when the code length N is 1024, and the consumption numbers of the hardware resource indicator lookup table (LUT) and flip-flops (FF) are 5.7% and 10% of that of the linear structure decoder, respectively. Further satellite-to-ground QKD data reconciliation simulation experiments show that under the conditions of typical system parameters, when the code length is 64 K, the security rate of the decoder can reach 27.9 kbit/s.}