The successful exfoliation of monolayer graphene^[1] initiated large-scale studies of two-dimensional (2D) materials, which have no dangling bonds, atomic thickness,^[2] and van der Waals interactions.^[3] To extend Moore’s law, 2D materials with these characteristics have been applied to a variety of applications in integrated circuits, such as logic gates,^[4] memories,^[5] and central processing units.^[6] However, these applications generally rely on traditional CMOS-based structures and follow the development methods of silicon-based circuits, which cannot take full advantage of the natural properties of 2D materials. Recently, a work innovatively constructed a 2D logic transistor with a new working principle,^[7] implementing logic calculation in one single transistor, which saves 50% area in one unit. The logic gate of the traditional structure requires at least two transistors to realize the same logic calculation. This new working mechanism transistor not only shows a promising solution for future 2D electronic devices and circuit architectures, but also increases 2D integrated circuit density. For further application of this 2D logic transistor, further research is required on logical function modulated by multiple physical fields, especially the working temperature.

In this work, a full 2D logic transistor with a sandwich structure (h-BN/MoS₂/h-BN) is fabricated and its logic output at various environmental temperatures is measured. As the temperature changes, the logic output of the transistor switches between two output functions (‘AND’ and ‘OR’), which means 2D logic transistors have application potential in extreme environments. This temperature switchable phenomenon is attributed to the modulation of temperature to energy band, specifically to mobility and threshold voltage. To confirm this explanation, detailed experimental data and theoretical calculations are provided.

To study the temperature dependent characteristic of a MoS₂ logic transistor, a device was fabricated on an Al₂O₃ substrate, and measured by cryogenic probe station with a temperature range of 7 K to 250 K. Firstly, multilayer MoS₂ and h-BN were exfoliated with tapes on a sacrificial layer. Then, wet transfer method was used to stack the sandwich structure layer by layer. Next, electron beam lithography was applied to define the location of electrodes, especially the full alignment of the bottom and top gates, in case of non-overlapping region appearance. Finally, a 5 nm Cr (adhesion layer) and a 30 nm Au (metal) layer were deposited as electrodes by electron beam evaporator. The temperature dependence of the electrical characteristic was measured in a vacuum, while fabrication processes were realized in the normal atmosphere. The thickness of h-BN was confirmed by atomic force microscope (Fig. A1): top dielectric was 6 nm; bottom dielectric was 8 nm; thickness of channel material MoS₂ was around 5–6 nm; channel width and length were 3 μm and 8.5 μm, respectively.

Figure 1(a) presents a three-dimensional schematic structure of the MoS₂ logic transistor: MoS₂ is the channel layer, connecting with the drain and source electrodes; h-BN is the dielectric layer, blocking the connection between the gate and channel; the gates serve as the terminals of signal input, IN 1 for the top gate and IN 2 for the bottom gate. When inputs of IN 1 and IN 2 are low voltages, the input signal of the device is defined as IN-00. When either input of IN 1 and IN 2 is a high voltage, the input signal of the device is defined as IN-10 or IN-01. When inputs of IN 1 and IN 2 are high voltages, the input signal of the device is defined as IN-11. The high output current of the MoS₂ logic transistor is defined as ‘1’ state, while low output current is ‘0’ state. The false-colored scanning electron microscope (SEM) image of the real device is shown in Fig. A2, which shows an accurate alignment of the two gates. A previous study^[8] showed that MoS₂ exhibits high electron mobility^[9] and a large band gap,^[10] which indicates that MoS₂ has the potential to meet the requirements of logical application. The components of channel and dielectric are confirmed by Raman spectroscopy (Fig. 1(b)), which shows two characteristic peaks (A_1g, E_2g) of MoS₂^[11] and one characteristic peak of h-BN.^[12] When a series of identical input signals are applied to a logic transistor (IN-00, IN-01, IN-10, IN-11, voltage amplitude of 2 V), the channel current exhibits outputs of logic ‘AND’ at low temperature (10 K) and ‘OR’ at high temperature (250 K), revealing the temperature-switching characteristic of the MoS₂ logic transistor, as shown in Fig. 1(c). Due to the structure and working principle of the transistor, the directly measured output signal of the MoS₂ logic transistor is current. The circuit of the voltage-in current-out test system is plotted in Fig. A3. To transfer the current signal into a voltage signal, an additional resistor is introduced into the testing system and transforms the channel current into its partial voltage, as shown in Fig. A4. Figure A5 is the partial voltage of the resistor (R = 220 kΩ), showing a recognizable voltage-in voltage-out ‘OR’ logic gate function. Since the current output can be simply transferred into voltage, we take the current signal as evaluation criteria in the following part of this article.

When the input voltages of the bottom gate (V_BG) and top gate (V_TG) are plotted as x- and y-axis, respectively, the output of current distribution density mapping can be divided into four regions, IN-00, IN-01, IN-10, and IN-11, obtained by drain voltage (V_D) of 500 mV. The mean value of the output channel current is selected as the output state and is used as the parameter to transform output state into a color squire, and four color-squires are composed together as one part to illustrate the logic function of the MoS₂ logic transistor at different temperatures. The basic color squires are blue (R = 0, G = 0, B = 255) and red (R = 255, G = 0, B = 0), representing the current values 1 pA and 1 μA. At 10 K, only the IN-11 region is in red, corresponding with logic ‘AND’, which means the channel can only be opened when both gates input high voltages. With the increase of temperature (at 150 K), the color of region IN-10 begins to turn red, which means the device is in a transition state of logical function. When the temperature rises to 250 K, the color of three regions (IN-01, IN-10, IN-11) turns to red, corresponding with logic ‘OR’, which means the channel can be opened by either gate (Fig. 2(a)). Extracting the average value of current in four stages at different temperatures, we plot Fig. 2(b). When the temperature increases, the output current of regions IN-00 and IN-11 is stable, whereas the output current of regions IN-10 and IN-01 changes, which leads to the transformation of logic output. This shows a dynamic change process of temperature-switching phenomenon.

Figure 2 indicates that the key element of logical transformation is the output transformation of regions IN-01 and IN-10. The transformation mechanism can be demonstrated by the Fermi–Dirac distribution function. Figure 3(a) shows that the occupy probability of electrons, symbolized as f(E), increases with the increase of temperature. In f(E) = 1/{exp[(E – E_F)/kT] + 1}, f(E) is affected by two factors: one is E – E_F, standing for the band gap variation, the other is kT, standing for the extra carrier energy provided by temperature. With the increase of temperature, the increase of kT leads the increase of f(E), which means the probability of electron occupation in E_c is higher. Besides kT directly affected by temperature, E – E_F is also impacted by temperature. Previous studies showed that the band gap of MoS₂ decreases with the increase of temperature.^[13,14] Figure 3(b) is the photoluminescence spectrum of the MoS₂ logic transistor at different temperatures, which shows a significant indirect band gap shift from 1.581 eV at 10 K to 1.535 eV at 250 K and direct band gap shift from 1.939 eV at 10 K to 1.862 eV at 250 K (Fig. 3(c)). Based on the band gap variation phenomenon, E – E_F shows a decreasing tendency with the increase of temperature, which also leads to an increase of f(E). So the two aspects have the same increase tendency for f(E), which means higher temperature generates a higher probability of electron occupation in the bottom of conduction band E_c, corresponding to Fig. 3(a). Therefore, the temperature switchable phenomenon is caused by the band gap variation and carrier energy directly provided by temperature. Furthermore, figure A6 presents the dual-sweep transfer curves of the top and bottom interfaces, which shows negligible hysteresis of electrical characteristics caused by charge trapping. So, the influence of charge trapping/releasing effect on channel current can be ignored.

After analyzing the transition principle of logical output in a dual gate MoS₂ transistor, figure 4 further illustrates the temperature-dependent current characteristics with detailed experimental data. The channel current is calculated by theoretical equations under different drain voltage conditions. The following equations (1) and (2) apply to the linear region and saturated region, respectively:

$$ \begin{eqnarray}\begin{array}{lll}{I}_{{\rm{D}}} & = & \displaystyle \frac{1}{2}\mu {C}_{{\rm{ox}}}\displaystyle \frac{W}{L}[2({V}_{{\rm{G}}}-{V}_{{\rm{T}}}){V}_{{\rm{D}}}-{V}_{{\rm{D}}}^{2}],\,0\lt {V}_{{\rm{D}}}\lt {V}_{{\rm{G}}}-{V}_{{\rm{T}}},\,\,\,\,\,\end{array}\end{eqnarray}$$ (1)

$$ \begin{eqnarray}\begin{array}{lll}{I}_{{\rm{D}}} & = & \displaystyle \frac{1}{2}\mu {C}_{{\rm{ox}}}\displaystyle \frac{W}{L}{({V}_{{\rm{G}}}-{V}_{{\rm{T}}})}^{2},\,\,\,{V}_{{\rm{D}}}\gt {V}_{{\rm{G}}}-{V}_{{\rm{T}}},\end{array}\end{eqnarray}$$ (2)

The transistor mobility is extracted from

$$ \begin{eqnarray}{g}_{{\rm{m}}}=\mu {C}_{{\rm{ox}}}\displaystyle \frac{W}{L}{V}_{{\rm{D}}},\end{eqnarray}$$ (3)

With 2D materials, the logic function (‘OR’ and ‘AND’ gates) can be achieved in a single transistor. Compared with traditional transistor technology which needs at least two transistors to build a logic gate, this logic transistor architecture shows obvious area-efficiency strength. Furthermore, the temperature switchable phenomenon opens up the potential for tailor-made 2D circuits, such as reconfigurable circuits. In reconfigurable circuits, one circuit design can achieve more than one function in different temperature configurations. Therefore, temperature-switchable behavior will be helpful in tailor-made reconfigurable circuits based on 2D materials in the future. In this work, a colorful logic map (Fig. 2(a)) is proposed, which is helpful in the construction of a reconfigurable circuit.

In this work, we study the temperature dependence of an MoS₂ logic transistor, finding that the logical output result changes from ‘AND’ to ‘OR’ with the increase of temperature. The transformation of output between ‘AND’ and ‘OR’ at different temperatures is caused by the energy band gap decreasing and extra energy provided by temperature. With the increase of temperature, both direct and indirect band gaps of MoS₂ show a remarkable decrease, which is confirmed both by the photoluminescence spectrum and threshold voltage shift. The temperature switchable phenomenon of MoS₂ logic transistors has application prospects for extreme environments.