Electronics Optics & Control, Volume. 26, Issue 1, 73(2019)

Analysis on Test Result for SEU of FPGA in Simulated Low-Altitude Environment

GU Ze-ling... MEMG Ling-jun and REN Kai-fei |Show fewer author(s)
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    References(4)

    [7] [7] CIANI L, CATELANI M.A fault tolerant architecture to avoid the effects of Single Event Upset (SEU) in avionics applications[J].Measurement, 2014, 54(6):256-263.

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    [9] [9] KVAS M, VALACH S, FIEDLER P.Reliability and safety issues of FPGA based designs[J].IFAC Proceedings Volumes, 2012, 45(7):201-206.

    [10] [10] AZAMBUJA J R, KASTENSMIDT F, BECKER J.Configuration bitstream fault injection experimental results[M]//AZAMBUJA J R, KASTENSMIDT F, BECKER J.Hybrid fault tolerance techniques to detect transient faults in embedded processors.Berlin:Springer International Publishing, 2014:69-74.

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    GU Ze-ling, MEMG Ling-jun, REN Kai-fei. Analysis on Test Result for SEU of FPGA in Simulated Low-Altitude Environment[J]. Electronics Optics & Control, 2019, 26(1): 73

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    Paper Information

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    Received: Dec. 6, 2017

    Accepted: --

    Published Online: Jan. 19, 2019

    The Author Email:

    DOI:10.3969/j.issn.1671-637x.2019.01.016

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