Aiming at the requirements of high precision and low power consumption for CMOS image sensor, a 14bit column-level ADC was proposed. Based on the architecture of RAMP ADC, the two-step structure composed of 3-bit SAR ADC and 11-bit RAMP ADC was adopted, which reduced the quantization time effectively. In the module of RAMP ADC, the high-low clock counting method was employed to reduce the power consumption in the counting part. The correlated double sampling logic of RAMP-SAR-RAMP switch was proposed, which could decrease the number of SRAM and further reduce the layout area. Simulation results based on the 0.18μm standard CMOS process show that under the working mode of 600MHz clock and single edge counting, the quantization time of ADC is 9.32μs, and the average power consumption in the counting part is 8.51μW under the 1.8V digital power supply.