Semiconductor Optoelectronics, Volume. 42, Issue 1, 106(2021)

A Design of All Digital Phase Locked Loop in Image Sensors

FENG Guolin... CHANG Yuchun* and MA Yanhua |Show fewer author(s)
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    References(6)

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    [2] [2] Wang B, Liu Y H, Harpe P, et al. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40nm CMOS[C]// Proc. IEEE Inter. Symp. on Circuits and Systems (ISCAS), 2015: 24-27.

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    FENG Guolin, CHANG Yuchun, MA Yanhua. A Design of All Digital Phase Locked Loop in Image Sensors[J]. Semiconductor Optoelectronics, 2021, 42(1): 106

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    Paper Information

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    Received: Dec. 3, 2020

    Accepted: --

    Published Online: Mar. 18, 2021

    The Author Email: Yuchun CHANG (cyc@dlut.edu.cn)

    DOI:10.16818/j.issn1001-5868.2021.01.019

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