Aiming at the problems of high power consumption, high jitter and long locking-time of traditional phase-locked loops (PLL) in image sensors, a kind of fractional frequency all-digital phase locked loop (ADPLL) is proposed based on a counter architecture. It realizes low power consumption, low noise, low jitter and fast locking design. First of all, the dynamic adjustment lock control algorithm is adopted to reduce the loop noise and shorten the locking time. Secondly, a universal unit is designed to realize the integration of digital time converter (DTC) and time digital converter (TDC), reducing the jitter caused by the gain mismatch. Simulation results based on 180nm CMOS process show that the ADPLL can achieve frequency output in the range of 250MHz~2.8GHz under 1.8V power supply voltage, the locking time is 1.028μs. When the offset carrier frequency is 1MHz, the phase noise is -102.249dBc/Hz, and the root mean square jitter is 1.7ps.