[1] [1] RAMKAJ A T, PENA RAMOS J C, PELGROM M J M, et al. A 5-GS/s 158.6-mW 9.4-ENOB passive-sampling time-interleaved three-stage pipelined-SAR ADC with analog-digital corrections in 28-nm CMOS ［J］. IEEE J Sol Sta Circ, 2020, 55(6): 1-12.

[2] [2] FAZEL Z, SAEEDI S, ATARODI M. Pipelining method for low-power and high-speed SAR ADC design ［J］. Analog Integr Circ Sig Process, 2016, 87(3): 353-368.

[3] [3] ZHOU Y, XU B, CHIU Y. A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector ［J］. IEEE J Sol Sta Circ, 2015, 50(4): 920-931.

[4] [4] SEHGAL R, VAN DER GOES F, BULT K. A 13 mW 64 dB SNDR 280 MS/s pipelined ADC using linearized open-loop class-AB amplifiers ［C］// IEEE ESSCIRC. Leuven, Belgium. 2017: 131-134.

[6] [6] WU C, YUAN J. A 12-bit, 300-MS/s single-channel pipelined-SAR ADC with an open-loop MDAC ［J］. IEEE J Sol Sta Circ, 2019, 54(5): 1446-1454.

[7] [7] XIE Y, LIANG Y, LIU M, et al. A 10-bit 5 MS/s VCO-SAR ADC in 0.18 μum CMOS ［J］. IEEE Trans Circ & Syst II: Expr Bri, 2019, 66(1): 26-30.

[8] [8] LIU C. A 0.35 mW 12 b 100 MS/s SAR-assisted digital slope ADC in 28 nm CMOS ［C］// IEEE ISSCC. San Francisco, CA, USA. 2016: 462-463.

[9] [9] LIU H, LIU M, ZHU Z, et al. A high linear voltage-to-time converter (VTC) with 1.2 V input range for time-domain analog-to-digital converters ［J］. Microelectronics J, 2019, 88(6): 18-24.

[10] [10] ZHU Y, CHAN C, SIN S, et al. A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation ［J］. IEEE J Sol Sta Circ, 2012, 47(11): 2614-2626.

[11] [11] CHEN Y, HSIEH C. A 0.4 V 2.02 fJ conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90 nm CMOS ［C］// VLSI CDTP. Honolulu, HI, USA. 2014: 357-364.

[12] [12] ZHANG M, CHAN C, ZHU Y, et al. A 0.6-V 13-bit 20-MS/s two-step TDC-assisted SAR ADC with PVT tracking and speed-enhanced techniques ［J］. IEEE J Sol Sta Circ, 2019, 54(12): 3396-3409.

[13] [13] ZHAO H, DAI F F. A 0.97 mW 260 MS/s 12 b pipelined-SAR ADC with ring-TDC-based fine quantizer for PVT robust automatic cross-domain scale alignment ［C］// IEEE ISSCC. San Francisco, CA, USA. 2022: 166-167.

[15] [15] OHHATA K. A 2.3-mW, 1-GHz, 8-bit fully time-based two-step ADC using a high-linearity dynamic VTC ［J］. IEEE J Sol Sta Circ, 2019, 54(7): 2038-2048.