In order to meet the requirement of high speed and high precision sampling under low voltage conditions, a voltage-time domain two-stage hybrid structure pipeline analog-to-digital converter (ADC) was designed. The first stage of the pipeline ADC, which was a successive approximation type (SAR) ADC, converted the voltages into 8 bit digital signals. After the residual voltage was transformed into time-domain delay information, the second stage 4.5 bit time-to-digital converter (TDC) converted the delay information, and the final calibrated output achieved 12 bit precision conversion. By using multiple voltage supplies, improving residual voltage transfer and amplifier structure, and optimizing the time decider, the dynamic performance and sampling speed of the ADC has been improved, and the sampling power consumption has been reduced. The ADC was designed and simulated in a 40 nm CMOS process. The power consumption is 9.5 mW at a sampling rate of 200 MS/s, the dynamic indexes SNDR, SFDR is 68.4 dB, 83.6 dB respectively, and the figure of merit 22 pJ·conv-1·step-1 , which can meet the application requirements of low power and high speed sampling.