[1] [1] NOLL T G. Application specific eFPGAs for SoC platforms[C]// IEEE VLSI-TSA International Symposium on VLSI Design Automation and Test. Hsinchu,Taiwan,China:IEEE, 2005:348.

          NOLL T G. Application specific eFPGAs for SoC platforms[C]// IEEE VLSI-TSA International Symposium on VLSI Design Automation and Test. Hsinchu,Taiwan,China:IEEE, 2005:348.

[2] [2] ACHRONIX Corp. Achronix product brief[EB/OL]. (2019-01)[2019-04]. https://www.achronix.com/wp-content/uploads/ 2017/05/Speedcore_ eFPGA_Product_BriefPB028.pdf.

          ACHRONIX Corp. Achronix product brief[EB/OL]. (2019-01)[2019-04]. https://www.achronix.com/wp-content/uploads/ 2017/05/Speedcore_ eFPGA_Product_BriefPB028.pdf.

[3] [3] FLEXLOGIX Corp. Embedded FPGA basics[EB/OL]. (2018-06)[2019-04]. http://www.flex-logix.com/fpga-tutorial.html.

          FLEXLOGIX Corp. Embedded FPGA basics[EB/OL]. (2018-06)[2019-04]. http://www.flex-logix.com/fpga-tutorial.html.

[4] [4] VENUGOPAL N,MANIMEGALAI R. Survey on FPGA routing techniques[J]. International Journal on Computer Science and Engineering(IJCSE). 2012,4(7):1304-1309.

          VENUGOPAL N,MANIMEGALAI R. Survey on FPGA routing techniques[J]. International Journal on Computer Science and Engineering(IJCSE). 2012,4(7):1304-1309.

[5] [5] MCMURCHIE L,EBELING C. PathFinder:a negotiation-based performance-driven router for FPGAs[C]// Third International ACM Symposium on Field-Programmable Gate Arrays. Napa Valley,USA:[s.n.], 1995:111–117.

          MCMURCHIE L,EBELING C. PathFinder:a negotiation-based performance-driven router for FPGAs[C]// Third International ACM Symposium on Field-Programmable Gate Arrays. Napa Valley,USA:[s.n.], 1995:111–117.

[8] [8] ROSE J,LUU J,YU C W,et al. The VTR project: architecture and CAD for FPGAs from Verilog to routing[C]// 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays(FPGA). Monterey,USA:[s.n.], 2012:77-86.

          ROSE J,LUU J,YU C W,et al. The VTR project: architecture and CAD for FPGAs from Verilog to routing[C]// 20th ACM/SIGDA International Symposium on Field Programmable Gate Arrays(FPGA). Monterey,USA:[s.n.], 2012:77-86.

[9] [9] BETZ V,ROSE J. Automatic generation of FPGA routing architectures from high-level descriptions[C]// ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM,New York,NY:[s.n.], 2008:175-184.

          BETZ V,ROSE J. Automatic generation of FPGA routing architectures from high-level descriptions[C]// ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM,New York,NY:[s.n.], 2008:175-184.

[10] [10] LI Zhihua,YANG Haigang,YANG Liqun,et al. Architecture model and resource graph building algorithm for detailed FPGA architecture design[J]. Journal of Electronics(China), 2014,31(6):505–512.

          LI Zhihua,YANG Haigang,YANG Liqun,et al. Architecture model and resource graph building algorithm for detailed FPGA architecture design[J]. Journal of Electronics(China), 2014,31(6):505–512.

[11] [11] COENEN T,SCHLEIFER J,WEIB O,et al. Interconnect routing of embedded FPGAs using standard VLSI routing tools[C]//International Symposium on System on Chip. Tampere,Finland:IEEE, 2010:121-124.

          COENEN T,SCHLEIFER J,WEIB O,et al. Interconnect routing of embedded FPGAs using standard VLSI routing tools[C]//International Symposium on System on Chip. Tampere,Finland:IEEE, 2010:121-124.

[12] [12] NEUMANN B,SYDOM T,BLUME H,et al. Design flow for embedded FPGAs based on a flexible architecture template[C]// Design,Automation & Test in Europe. Munich,Germany:IEEE, 2008:56-61.

          NEUMANN B,SYDOM T,BLUME H,et al. Design flow for embedded FPGAs based on a flexible architecture template[C]// Design,Automation & Test in Europe. Munich,Germany:IEEE, 2008:56-61.

[13] [13] CHEN Xiaolin,LI Shuai,SCHLEIFER J,et al. High-level modeling and synthesis for embedded FPGAs[C]// Design, Automation & Test in Europe Conference & Exhibition. Grenoble,France:IEEE, 2013:1565-1570.

          CHEN Xiaolin,LI Shuai,SCHLEIFER J,et al. High-level modeling and synthesis for embedded FPGAs[C]// Design, Automation & Test in Europe Conference & Exhibition. Grenoble,France:IEEE, 2013:1565-1570.

[14] [14] KUON I,TESSIER R,ROSE J. FPGA architecture:survey and challenges[J]. Foundations and Trends in Econometrics, 2008,2(2):135-253.

          KUON I,TESSIER R,ROSE J. FPGA architecture:survey and challenges[J]. Foundations and Trends in Econometrics, 2008,2(2):135-253.

[15] [15] WILLIAMS S. Icarus verilog[EB/OL]. (2016-08)[2019-04]. http://iverilog.icarus.com/index.html.

          WILLIAMS S. Icarus verilog[EB/OL]. (2016-08)[2019-04]. http://iverilog.icarus.com/index.html.