During each iteration of embedded Field Programmable Gate Array(eFPGA) customization process, router has to be run on a new Route Resource Graph(RRG) for the new architecture in order to meet design constraints in many aspects, such as area and timing. Conventional eFPGA RRG modeling method regenerates the whole chip’s architecture description and builds routing nodes and edges based on it in every evaluation iteration. However, the efficiency of this method suffers from the rising scale of the chip being evaluated. A module-based RRG modeling method is proposed to address this problem. It firstly builds RRG for every module type and models interconnect relations among them, after that, stitches them together according to the device resource arrangement. It depends on a relatively small database, reduces the modeling runtime and memory peak footprint by around 84% and 64% respectively and thereby improves the eFPGA evaluation efficiency.