[4] [4] TIWARI R K, SAINI I. Design of a low-level offset op amp using ping pong auto zeroing architecture ［C］// First International Conference on Advances in Computing and Future Communication Technologies (ICACFCT). Meerut, India. 2021: 263-268.

[5] [5] WITTE J F, MAKINWA K A A, HUIJSING J H. A CMOS chopper offset-stabilized opamp ［J］. IEEE Journal of Solid-State Circuits, 2007, 42(7): 1529-1535.

[6] [6] BORTUN N, STAN M N, BREZEANU G. High precision bidirectional chopper amplifier with extended common mode input voltage range ［C］// International Semiconductor Conference (CAS). Sinaia, Romania. 2015: 297-300.

[7] [7] SCHAFFER V, SNOEIJ M F, IVANOV M V, et al. A 36 V programmable instrumentation amplifier with sub-20 μV offset and a CMRR in excess of 120 dB at all gain settings ［J］. IEEE Journal of Solid-State Circuits, 2009, 44(7): 2036-2046.

[8] [8] WITTE J F, HUIJSING J H, MAKINWA K A A. A chopper and auto-zero offset-stabilized CMOS instrumentation amplifier ［C］// Symposium on VLSI Circuits. Kyoto, Japan. 2009: 210-211.

[11] [11] KUSUDA Y. A 60 V auto-zero and chopper operational amplifier with 800 kHz interleaved clocks and input bias current trimming ［J］. IEEE Journal of Solid-State Circuits, 2015, 50(12): 2804-2813.

[12] [12] FAN Q, HUIJSING J H, MAKINWA K A A. A capacitively-coupled chopper operational amplifier with 3 μV offset and outside-the-rail capability ［C］// ESSCIRC. Bordeaux, France. 2012: 73-76.

[13] [13] SNOEIJ M F, IVANOV M V. A 36 V JFET-input bipolar operational amplifier with 1 μV/°C maximum offset drift and -126 dB total harmonic distortion ［C］// IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2011: 248-250.