Fig. 1. Confinement potential induced by ionizing impurity^[19]. 电离杂质形成的势阱结构^[19]

Fig. 2. Structure and schematic diagram of the ideal single-dopant transistor: (a) Schematic illustration of single-dopant transistor; (b) donor mediates single-electron tunneling from source to drain; (c) transfer characteristics for single-dopant transistor in the low temperature^[25]. 理想单杂质晶体管的基本结构和工作原理图　(a)单杂质晶体管结构示意图; (b)施主原子调制源端到漏端的单电子隧穿; (c)低温下单杂质晶体管的转移特性曲线^[25]

Fig. 3. (a) Perspective STM image of single-atom transistor; (b) close-up of the inner device area^[28]. (a)单原子晶体管器件结构 STM 图像; (b)局部放大图^[28]

Fig. 4. (a) Schematic channel structure; (b) example of simulated potential profile; (c) example of dc I_sd -V_g characteristics (V_sd = 5 mV) for a short-channel FET; (d) schematic channel structure; (e) example of simulated potential profile; (f) example of dc I_sd -V_g chara-cteristics (V_sd = 5 mV) for a long-channel FET^[29]. (a)短沟道器件示意图; (b)短沟道器件电势分布图; (c)短沟道器件I_sd -V_g特性曲线(V_sd = 5 mV); (d)长沟道器件示意图; (e)长沟道器件电势分布图; (f)长沟道器件I_sd -V_g特性曲线(V_sd = 5 mV)^[29]

Fig. 5. (a) Statistical results of the number of subpeaks; (b) statistical results of the number of dopant-induced QDs; (c) average number of dopants embedded in one QD for 50 nm × 50 nm nanostructures^[29]. (a)不同沟道长度下分裂峰个数的实验统计; (b)不同沟道长度下量子点个数的模拟统计; (c) 50 nm × 50 nm纳米结构中一个量子点中的平均杂质数目^[29]

Fig. 6. (a) Sequence of electronic potential landscapes as a function of applied V_BG; (b) a simple illustration of one-by-one neutralization of individual P-donors at different V_BG^[30]. (a)低温下随栅压变化的电势分布图; (b)分立的磷施主原子在不同栅压下逐个电中性化^[30]

Fig. 7. (a) Low-temperature source-drain current (I_D) vs. gate voltage (V_G) characteristics; (b) one possible P-donors’ distribution and schematic channel potential profiles^[31]. (a) SOI-FET低温下的I_D-V_G特性曲线; (b)沟道中可能的杂质原子分布以及沟道电势分布示意图^[31]

Fig. 8. Tailed localized states in disordered systems^[32]. 无序系统中的带尾定域态^[32]

Fig. 9. Schematic representation of the energy and space distribution of the localized states in the case of weak (a) and strong (b) compensation^[34]. 弱杂质补偿和强杂质补偿情况下的能带和定域态空间分布示意图　(a)弱杂质补偿; (b)强杂质补偿^[34]

Fig. 10. Hopping modes of the electron: (a) Variable range hopping; (b) nearest neighbor hopping^[38]. 电子的跃迁方式　(a)可变程跃迁; (b)最近邻跃迁^[38]

Fig. 11. (a) Schematic of KPFM measurement setup; (b), (c) potential distribution of donor atoms at different doping concentrations^[39](a)开尔文探针力显微镜测量SOI-FETs的结构示意图; (b), (c)不同掺杂浓度下, 施主原子形成的电势分布图^[39]

Fig. 12. (a) Low-temperature source-drain current (I_D) vs gate voltage (V_G) characteristics; (b) a possible P-donors’ distribution and schematic channel potential profiles in the selective doping channel^[31]. (a) SOI-FET低温下的I_D-V_G特性曲线; (b)选择性掺杂沟道中可能的杂质原子分布以及沟道电势分布示意图^[31]

Fig. 13. Hubbard band model^[43]. Hubbard能带模型^[43]

Fig. 14. Anderson-Mott transition probed by means of quantum transport^[44]. 不同杂质数目下的量子输运特征, 从单施主态到杂质带的安德森-莫特转变^[44]

Fig. 15. (a) An idealized representation of the potential distributions in the 20 phosphorous donors distributed along the channel of the sample; (b) conductance σ of the device probed at 4.4 K measured at V_ds = 2.505 mV. Inlet: extraction of the threshold voltage at room temperature, at V_ds = 2.505 mV^[45]. (a)沿沟道分布的20个磷施主原子中电势分布的理想示意图; (b)V_ds = 2.505 mV时, 在4.4 K下测量的器件电导-栅压曲线. 插图: V_ds = 2.505 mV时, 室温下提取的阈值电压^[45]

Fig. 16. (a) The conductance as a function of the gate voltage V_g from 4.2 to 274 K; (b) the thermal activation of the upper Hubbard band at high temperature; (c) the thermal activation of the lower Hubbard band at low temperature; (d) the thermal activation of the upper Hubbard band at low temperature^[45]. (a)4.2—274 K温度区间下的电导-栅压曲线; (b)高温下上Hubbard带的热激活输运; (c)低温下下Hubbard带的热激活输运; (d)低温下上Hubbard带的热激活输运^[45]

Fig. 17. (a) Schematic configuration of the fabricated Si SET; (b) scanning electron microscopy image of the Si nanowire after chemical wet-etching; (c) transmission electron microscopy image of the Si nanowire after fabricating the GAA structure; (d) I_D−V_G characteristic curves of the fabricated SET at T = 150−300 K^[52]. (a)单电子晶体管结构示意图; (b)化学湿法腐蚀后硅纳米线扫描电子显微镜(SEM)图; (c)形成围栅GAA结构后硅纳米线透射电子显微镜(TEM)图; (d)制备的单电子晶体管在150−300 K下的I_D-V_G特性曲线^[52]

Fig. 18. (a) Schematic of dopant atom transistor; (b) two determined levels provided by impurity in device^[19]. (a)杂质原子晶体管结构示意图; (b)杂质在器件沟道中提供确定的两个能级^[19]

Fig. 19. Ground state of phosphorous donor becomes deeper with decreasing radius of Si nanowire^[53]. 磷原子的基态能级随硅纳米线直径的减小而加深^[53]

Fig. 20. Ionization energy E_I vs. the wire radius R for donor impurities: (a) Without dielectric confinement; (b) with dielectric confinement^[55]. (a)没有和(b)有介电限制时杂质原子的电离能随纳米线半径的变化曲线图^[55]

Fig. 21. (a) Schematic of SOI transistor; (b) TEM image taken across the device channel; (c) SEM images of non-stub channel and (d) stub channel^[57]. (a) SOI晶体管结构示意图; (b)器件沟道TEM图; (c)原纳米线结构; (d) stub纳米线结构^[57]

Fig. 22. Binding energy of clustered donors is shown for different N^[53]. 基态电子的束缚能随耦合原子数目的增加而增大^[53]

Fig. 23. (a) The selectively-doped Si nanoscale channel; (b) atomistic representation of the potential landscape simulated for a selectively-doped area with deepest potential well^[58]. (a)选择性掺杂硅纳米沟道; (b)选择性掺杂区域模拟的最深势阱分布^[58]

Fig. 24. (a) and (b) IDS-VG characteristics as a function of temperature for a selectively-doped-channel SOI-FET (up to 300 K) and for a non-doped-channel SOI-FET (up to 160 K)^[58]. (a)沟道选择性掺杂和(b)沟道未掺杂SOI-FET在不同温度下的I_D-V_G特性曲线^[58]

Fig. 25. (a) I_DS-V_G characteristics as a function of temperature for the selectively-doped channel SOI-FET; (b) effective barrier height (E_Beff) estimated from Arrhenius plots as a function of V_G; (c) arrhenius plots for V_G corresponding to different peaks; (d) schematic illustrations of the mechanism of Coulomb blockade of activated conduction for the single-electron tunneling current peak (lower panel) and for the Coulomb blockade condition with an electron trapped in the QD (upper panel); (e) E_Beff extracted for a non-doped-channel SOI-FET, exhibiting only behavior typical of thermally-activated conduction^[58]. (a)不同温度下, 沟道选择性掺杂SOI-FET器件I_DS-V_G特性曲线; (b)有效势垒高度随栅压V_G的变化; (c)不同电流峰对应的Arrhenius曲线; (d)激活传导的库仑阻塞机制(下图), 量子点俘获电子的库仑阻塞情形(上图); (e)沟道未掺杂SOI-FET器件仅仅表现出热激活传导性质^[58]

Fig. 26. (a) Schematic of the point contact QD transistor; (b) schematic representation of the energy diagram across the point-contact region^[62]. (a)点接触式量子点晶体管结构示意图; (b)点接触区域的能带示意图^[62]