Semiconductor Optoelectronics, Volume. 44, Issue 3, 344(2023)

A Full-Rate Linear 25 Gbps Clock and Data Recovery Circuit

ZHANG Shuhao... HUANG Qijun, CHANG Sheng, WANG Hao and HE Jin* |Show fewer author(s)
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    References(11)

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    [3] [3] Chen W M, Yao Y S, Liu S L. A 10.4-16 Gb/s reference-less baud-rate digital CDR with one-tap DFE using a wide-range FD[J]. IEEE J. of Solid-State Circuits, 2021, 68(11): 4566-4575.

    [4] [4] Lee Y S, Ho W H, Chen W Z. A 25-Gb/s, 2.1-pJ/bit, fully integrated optical receiver with a baud-rate clock and data recovery[J]. IEEE J. of Solid-State Circuits, 2019, 54(8): 2243-2254.

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    [6] [6] Rahman W, Yoo D, Liang J, et al. A 22.5-to-32-Gb/s 3.2-pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28-nm CMOS[J]. IEEE J. of Solid-State Circuits, 2017, 52(12): 3517-3531.

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    ZHANG Shuhao, HUANG Qijun, CHANG Sheng, WANG Hao, HE Jin. A Full-Rate Linear 25 Gbps Clock and Data Recovery Circuit[J]. Semiconductor Optoelectronics, 2023, 44(3): 344

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    Paper Information

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    Received: Feb. 21, 2023

    Accepted: --

    Published Online: Nov. 26, 2023

    The Author Email: Jin HE (jin.he@whu.edu.cn)

    DOI:10.16818/j.issn1001-5868.2023022102

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