In this paper, a full-rate linear 25 Gbps clock and data recovery circuit (CDRC) is proposed for the application of high-speed optical communication systems. To achieve full-rate clock extraction and data recovery, CDRC employed a mixer-based linear phase detector and automatic frequency locking technique. No external reference clock was used in the design. Based on a 45 nm CMOS process, the CDR circuit from the post-plate simulation results achieves that the peak-to-peak differential voltage Vpp and peak-to-peak jitter of the recovered 25 Gbps data eye diagram are 1.3 V and 2.93 ps, respectively. The output 25 GHz clock has a differential peak-to-peak voltage Vpp and peak-to-peak jitter of 1 V and 2.51 ps, respectively, with phase noise of -93.6 dBc/Hz@1 MHz. The chip has an area of 1.18×1.07 mm2 and consumes 51.36 mW at a supply voltage of 1 V.