[2] [2] WEI H, CHAN C, CHIO U. et al. An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC ［J］. IEEE Journal of Solid-State Circuits, 2012, 47(11): 2763-2772.

[3] [3] ZHA Y, ZAHND L, DENG J, et al. An untrimmed PVT-robust 12-bit 1-MS/s SAR ADC IP in 55 nm deeply depleted channel CMOS process ［C］ // 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC). Macau, China. 2019: 13-16.

[4] [4] CHUNG Y H, YEN C W, WU M H. A 24-μW 12-bit 1-MS/s SAR ADC with two-step decision DAC switching in 110-nm CMOS ［J］. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(11): 3334-3344.

[5] [5] AHN S, SONG J, LIM C, et al. A 1 MS/s 915 ENOB low-power SAR ADC with triple-charge-sharing technique ［C］ // 2020 International SoC Design Conference (ISOCC). Yeosu, Korea. 2020: 1-2.

[6] [6] MCCREARY J L, GRAY P R. All-MOS charge redistribution analog-to-digital conversion techniques, I ［J］. IEEE Journal of Solid-State Circuits, 2003, 10(6): 371-379.

[7] [7] CONG L, BLACK W C. A new charge redistribution D/A and A/D converter technique - pseudo C-2C ladder. ［C］ // Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems. Lansing, MI, USA. 2000: 498-501.

[8] [8] BALASUBRAMANIAM H, GALJAN W, KRAU- TSCHNEIDER W H, et al. 12-bit hybrid C2C DAC based SAR ADC with floating voltage shield ［C］ // 2009 3rd International Conference on Signals, Circuits and Systems (SCS). Medenine, Tunisia. 2009: 1-5.

[9] [9] MCNEILL J A, CHAN K Y, COLN M C W, et al. All-digital background calibration of a successive approximation ADC using the “split ADC” architecture ［J］. IEEE Transactions on Circuits and Systems I: Regular Papers, 2011, 58(10): 2355-2365.

[11] [11] WANG T, LI H, MA Z, et al. A bypass-switching SAR ADC with a dynamic proximity comparator for biomedical applications ［J］. IEEE Journal of Solid-State Circuits, 2018, 53(6): 1743-1754.