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Infrared and Laser Engineering, Volume. 52, Issue 9, 20220896(2023)

Low-power and high-precision SPAD array readout circuit based on built-in clock

Lixia Zheng, Yongqi Han, Chenggong Wan, Mouzhao Zhou, Xuyan Li, Jin Wu, and Weifeng Sun*
Author Affiliations
  • School of Integrated Circuits, Southeast University, Wuxi 214125, China
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    AbstractGet PDF(in Chinese)
    Figures&Tables (11)
    Equations (2)
    References (15)
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    Figures & Tables(11)
    Single pixel architecture

    Fig. 1. Single pixel architecture

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    ROIC system structure

    Fig. 2. ROIC system structure

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    TDC clock signal timing. (a) Gated trigger; (b) Event-driven

    Fig. 3. TDC clock signal timing. (a) Gated trigger; (b) Event-driven

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    High-precision two-stage TDC circuit

    Fig. 4. High-precision two-stage TDC circuit

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    Four-level GRO structure

    Fig. 5. Four-level GRO structure

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    Improved pseudo-differential delay unit

    Fig. 6. Improved pseudo-differential delay unit

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    (a) CP-PLL 32 divides the output waveform; (b) GRO built-in clock function test; (c) PLL control voltage drive GRO built-in clock divide-by-16 waveform graph; (d) Divide-by-16 waveform of the GRO clock for input DC voltage

    Fig. 7. (a) CP-PLL 32 divides the output waveform; (b) GRO built-in clock function test; (c) PLL control voltage drive GRO built-in clock divide-by-16 waveform graph; (d) Divide-by-16 waveform of the GRO clock for input DC voltage

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    (a) TDC overall input-output curve; (b) TDC local input-output curve

    Fig. 8. (a) TDC overall input-output curve; (b) TDC local input-output curve

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    (a) DNL curve; (b) INL curve

    Fig. 9. (a) DNL curve; (b) INL curve

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    TDC array uniformity

    Fig. 10. TDC array uniformity

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    • Table 1. Performance comparison between the circuit in this paper and domestic and foreign design

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      Table 1. Performance comparison between the circuit in this paper and domestic and foreign design

      References2014[5]2017[6]2020[7]2022[8]This work
      Technology/nm180150150180180
      Voltage/V1.83.31.81.81.8
      Format64×6464×6432×3232×321×16
      ArchitectureVCROGROGROVCRO+PIGRO
      Pixel pitch/μm646044.6460100
      Resolution/ps145250210.250102
      Range/ns297205051.2100
      DNL/LSB±10.31.280.480.8
      INL/LSB1.71.21.922.181.3
      Power/mW9×10−3(pixel) <0.1(pixel)12.71.3(pixel’s VCRO)59.3
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    Lixia Zheng, Yongqi Han, Chenggong Wan, Mouzhao Zhou, Xuyan Li, Jin Wu, Weifeng Sun. Low-power and high-precision SPAD array readout circuit based on built-in clock[J]. Infrared and Laser Engineering, 2023, 52(9): 20220896

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    Paper Information

    Category: Infrared technology and application

    Received: Dec. 19, 2022

    Accepted: --

    Published Online: Oct. 23, 2023

    The Author Email: Sun Weifeng (swffrog@seu.edu.cn)

    DOI:10.3788/IRLA20220896

    Topics

    laser devices and laser physics
    Lasers and Laser Optics
    Laser physics
    laser manufacturing
    Instrumentation, Measurement and Metrology