Infrared and Laser Engineering, Volume. 52, Issue 9, 20220905(2023)

High frame rate target tracking method using domestic FPGA

Xiangjun Wang1,2 and Hui Zhu1,2
Author Affiliations
  • 1State Key Laboratory of Precision Measuring Technology and Instruments, Tianjin University, Tianjin 300072, China
  • 2MOEMS Education Ministry Key Laboratory, Tianjin University, Tianjin 300072, China
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    Figures & Tables(16)
    Schematic diagram of SMAD method
    Multistage pipelined adder
    Comparison before and after optimization of SMAD method
    Pyramid-like strategy
    Structural diagram of the target tracking platform
    Hardware architecture for maximum and minimum filtering
    Flowchart of the target search module
    Comparison of tracking indicators between SMAD and SAD
    Scale switching of the template
    Performance comparison of each template matching algorithm tracking the car sequence
    Functional simulation waveform of the target tracking module
    Tracking experiment for a target tracking system
    Anti-occlusion test of target tracking system
    • Table 1. Comparison of domestic and foreign FPGAs

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      Table 1. Comparison of domestic and foreign FPGAs

      MetricsForeign FPGADomestic FPGA
      TypesMoreFewer
      Process7 nm28 nm
      Gates100 millionMost: 10 million
      IP coresMoreFewer
      MarketHigh/mid/low endMid/low end
      TechnologyMatureImmature
      AutonomyPoorBetter
    • Table 2. Comparison of metrics for each tracking algorithm

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      Table 2. Comparison of metrics for each tracking algorithm

      Rotational deformationScale changePartial occlusionVarious scenarios
      Success rateAORSuccess rateAORSuccess rateAORSuccess rateAOR
      SAD0.76040.395480.80120.53640.74120.331760.76800.3818
      SSD0.75630.362190.77860.49970.74540.338790.75110.3695
      NCC0.75880.392480.75670.44040.73620.309510.74670.4228
      BSS0.76420.452650.83850.68170.784 70.506960.78510.4974
      DDIS0.768 30.456 250.82730.61880.78020.509 510.81970.5399
      SMAD-00.76400.441620.82610.55830.77750.481050.78420.4974
      SMAD0.76340.441860.859 40.682 10.77910.480600.829 40.540 6
    • Table 3. Resource consumption of the FPGA

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      Table 3. Resource consumption of the FPGA

      ResourcesConsumptionConsumption percentage
      LUTs4845772.76%
      Registers5858743.98%
      DRM36.523.55%
      I/O ports10234.00%
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    Xiangjun Wang, Hui Zhu. High frame rate target tracking method using domestic FPGA[J]. Infrared and Laser Engineering, 2023, 52(9): 20220905

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    Paper Information

    Category: Image processing

    Received: Dec. 29, 2022

    Accepted: --

    Published Online: Oct. 23, 2023

    The Author Email:

    DOI:10.3788/IRLA20220905

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