[1] [1] KATTMANN K, BARROW J. A technique for reducing differential non-linearity errors in flash A/D converters ［C］ // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 1991: 170-171.

[2] [2] SCHOLTENS P C S, VERTREGT M. A 6-b 16-Gsample/s flash ADC in 018 μm CMOS using averaging termination ［J］. IEEE Journal of Solid-State Circuits, 2002, 37(12): 1599-1609.

[3] [3] MIYAHARA M, MANO I, NAKAYAMA M, et al. A 22 GS/s 7b 274 mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers ［C］ // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2014: 388-389.

[4] [4] BULT K, BUCHWALD A. An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2 ［J］. IEEE Journal of Solid-State Circuits, 1997, 32(12): 1887-1895.

[6] [6] PAN H, ABIDI A A. Spatial filtering in flash A/D converters ［J］. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2003, 50(8): 424-436.

[7] [7] SIRIBURANON T, KONDO S, KIMURA K, et al. A 22 GHz-242 dB-FOM 42 mW ADC-PLL using digital sub-sampling architecture ［J］. IEEE Journal of Solid-State Circuits, 2016, 51(6): 1385-1397.

[8] [8] CHOI D, KIM D, CHO K, et al. A low noise 65nm 12 V 7-bit 1 GSPS CMOS folding A/D converter with a digital self-calibration technique ［C］ // International SoC Design Conference. Incheon, Korea. 2010: 194-197.

[9] [9] NAKAJIMA Y, SAKAGUCHI A, OHKIDO T, et al. A background self-calibrated 6 b 27 GS/s ADC with cascade-calibrated folding-interpolating architecture ［J］. IEEE Journal of Solid-State Circuits, 2010, 45(4): 707-718.

[10] [10] TAFT R C, FRANCESE P A, TURSI M R, et al. A 18 V 10 GS/s 10 b self-calibrating unified folding interpolating ADC with 91 ENOB at Nyquist frequency ［J］. IEEE Journal of Solid-State Circuits, 2009, 44(12): 3294-3304.