Microelectronics, Volume. 53, Issue 3, 492(2023)

n Overview of High Performance Comparators for Low Power SAR ADCA

YAO Yuhao and JIANG Mei
Author Affiliations
  • [in Chinese]
  • show less
    References(37)

    [1] [1] WANG H, WANG X Y, BARFIDOKHT A, et al. A battery-powered wireless ion sensing system consuming 55 nW of average power [J]. IEEE Journal of Solid-State Circuits, 2018, 53(7): 2043-2053.

    [2] [2] YOSHIOKA M, ISHIKAWA K, TAKAYAMA T, et al. A 10 b 50 MS/s 820 μW SAR ADC with on-chip digital calibration [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2010: 384-385.

    [4] [4] TANG X Y, LIU J X, SHEN Y, et al. Low-power SAR ADC design: overview and survey of state-of-the-art techniques [J]. IEEE Transactions on Circuits and Systems, 2022, 69(6): 2249-2262.

    [5] [5] ZHANG W P, TONG X Y. Noise modeling and analysis of SAR ADCs [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(12): 2922-2930.

    [6] [6] CHEN L, TANG X Y, SANYAL A, et al. A 07-V 06-μW 100-kS/s low-power SAR ADC with statistical estimation-based noise reduction [J]. IEEE Journal of Solid-State Circuits, 2017, 52(5): 1388-1398.

    [7] [7] ALLEN P E, HOLBERG D R. CMOS analog circuit design [M]. New York: Oxford University Press, 2002: 259-397.

    [8] [8] YUKAWA A. A CMOS 8-bit high-speed A/D converter IC [J]. IEEE Journal of Solid-State Circuits, 1985, 20(3): 775-779.

    [9] [9] TANG X Y, CHEN L, SONG J, et al. A 10-b 750 μW 200 MS/s fully dynamic single-channel SAR ADC in 40 nm CMOS [C] // 42nd European Solid-State Circuits Conference. Lausanne, Switzerland. 2016: 413-416.

    [11] [11] KHORAMI A, DASTJERDI M B, AHMADI A F. A low-power high-speed comparator for analog to digital converters [C] // IEEE International Symposium on Circuits and Systems. Montreal, Canada. 2016: 2010-2013.

    [12] [12] MASHHADI S B, LOTFI R. Analysis and design of a low-voltage low-power double-tail comparator [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(2): 343-352.

    [13] [13] SCHINKEL D, MENSINK E, KLUMPERINK E, et al. A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2007: 314-315.

    [14] [14] ELZAKKER M V, TUIJL E V, GERAEDTS P, et al. A 10-bit charge-redistribution ADC consuming 19 μW at 1 MS/s [J]. IEEE Journal of Solid-State Circuits, 2010, 45(5): 1007-1015.

    [15] [15] BINDRA H S, LOKIN C E, SCHINKEL D, et al. A 12-V dynamic bias latch-type comparator in 65-nm CMOS with 04-mV input noise [J]. IEEE Journal of Solid-State Circuits, 2018, 53(7): 1902-1912.

    [16] [16] TANG X Y, SHEN L X, KASAP B, et al. An energy-efficient comparator with dynamic floating inverter amplifier [J]. IEEE Journal of Solid-State Circuits, 2020, 55(4): 1011-1022.

    [17] [17] HERINSHA A J, SAM D S, ATCHAYA A J, et al. Design of low power dynamic comparator for SAR ADC [C] // 6th International Conference on Devices, Circuits and Systems. Coimbatore, India. 2022: 272-275.

    [18] [18] CANAL B, KLIMACH H, BAMPI S, et al. Hybrid comparator and window switching scheme for low-power SAR ADC [C] // IEEE 13th Latin America Symposium on Circuits and System. Santiago, Chile. 2022: 01-04.

    [19] [19] TANG X Y, YANG X X, LIU J X, et al. A 04-to-40 MS per s 757 dB-SNDR fully dynamic event-driven pipelined ADC with 3-Stage cascoded floating inverter amplifier [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2021: 376-378.

    [21] [21] SHIM M, JEONG S, MYERS P D, et al. Edge-pursuit comparator: an energy-scalable oscillator collapse-based comparator with application in a 741 dB SNDR and 20 kS/s 15 b SAR ADC [J]. IEEE Journal of Solid-State Circuits, 2017, 52(4): 1077-1090.

    [22] [22] MATHEW J P, KONG L, RAZAVI B. A 12-bit 200-MS/s 34-mW CMOS ADC with 085-V supply [C] // IEEE Symposium on VLSI Circuits. Kyoto, Japan. 2015: 66-67.

    [23] [23] AGNES A, BONIZZONI E, MALCOVATI P, et al. A 94-ENOB 1 V 38 μW 100 kS/s SAR ADC with time-domain comparator [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2008: 246-247.

    [24] [24] ZHOU X C, GUI X Y, GUSEV M, et al. A 12-bit 20-kS/s 640-nW SAR ADC with a VCDL-based open-loop time-domain comparator [J]. IEEE Transactions on Circuits and Systems, 2022, 6(92): 359-363.

    [25] [25] JIN J Y, GAO Y, SINENCIO E S. An energy-efficient time-domain asynchronous 2 b/step SAR ADC with a hybrid R-2R/C-3C DAC structure [J]. IEEE Journal of Solid-State Circuits, 2014, 49(6): 1383-1396.

    [26] [26] LEE S K, PARK S J, PARK H J, et al. A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface [J]. IEEE Journal of Solid-State Circuits, 2011, 46(3): 651-659.

    [27] [27] XIN X, HU Y H, TONG X Y. A 10-bit SAR ADC with adaptive VCO-based comparator for sensor chip [C] // IEEE International Conference on Integrated Circuits, Technologies and Applications. Zhuhai, China. 2021: 218-219.

    [28] [28] YOSHIOKA K. VCO-based comparator: a fully adaptive noise scaling comparator for high-precision and low-power SAR ADCs [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 29(12): 2143-2152.

    [29] [29] KAO C C, HSIEH S E, HSIEH C C. A 05-V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization [C] // IEEE Asian Solid-State Circuits Conference. Seoul, South Korea. 2017: 213-216.

    [30] [30] GIANNINI V, NUZZO P, CHIRONI V, et al. An 820 μW 9 b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS [C] // IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2008: 238-239.

    [31] [31] DING M, HARPE P, LIU Y H, et al. A 46 μW 13 b 64 MS/s SAR ADC with background mismatch and offset calibration [J]. IEEE Journal of Solid-State Circuits, 2017, 52(2): 423-432.

    [32] [32] HARPE P, CANTATORE E, ROERMUND A V. A 10 b/12 b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 101 b ENOB at 22 fJ/conversion-step [J]. IEEE Journal of Solid-State Circuits, 2013, 48(12): 3011-3018.

    [33] [33] MIKI T, MORIE T, MATSUKAWA K, et al. A 42 mW 50 MS/s 13 bit CMOS SAR ADC with SNR and SFDR enhancement techniques [J]. IEEE Journal of Solid-State Circuits, 2015, 50(6): 1372-1381.

    [34] [34] AHMADI M, NAMGOONG W. Comparator power reduction in low-frequency SAR ADC using optimized vote allocation [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(11): 2384-2394.

    [35] [35] AHMADI M, NAMGOONG W. Comparator power minimization analysis for SAR ADC using multiple comparators [J]. IEEE Transactions on Circuits and Systems, 2015, 62(10): 2369-2379.

    [36] [36] HUANG G Y, CHANG S J, LIU C C, et al. A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications [J]. IEEE Journal of Solid-State Circuits, 2012, 47(11): 2783-2795.

    [37] [37] GUERBER J, VENKATRAM H, GANDE M, et al. A 10-b ternary SAR ADC with quantization time information utilization [J]. IEEE Journal of Solid-State Circuits, 2012, 47(11): 2604-2613.

    [38] [38] WANG T Y, LI H Y, MA Z Y, et al. A bypass-switching SAR ADC with a dynamic proximity comparator for biomedical applications [J]. IEEE Journal of Solid-State Circuits, 2018, 53(6): 1743-1754.

    [39] [39] LIU C C, CHANG S J, HUANG G Y, et al. A 1 V 11 fJ/conversion-step 10 bit 10 MS/s asynchronous SAR ADC in 018 μm CMOS [C] // IEEE Symposium on VLSI Circuits. Honolulu, HI, USA. 2010: 241-242.

    [40] [40] DING Z M, ZHOU X, LI Q. A 05-11-V adaptive bypassing SAR ADC utilizing the oscillation-cycle information of a VCO-based comparator [J]. IEEE Journal of Solid-State Circuits, 2019, 54(4): 968-977.

    Tools

    Get Citation

    Copy Citation Text

    YAO Yuhao, JIANG Mei. n Overview of High Performance Comparators for Low Power SAR ADCA[J]. Microelectronics, 2023, 53(3): 492

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: Jul. 15, 2022

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220268

    Topics