Microelectronics, Volume. 53, Issue 5, 846(2023)

A Low Power Multi-Phase Clock Generation Circuit for TDC

GONG Hao, WANG Xiaolei, ZHOU Min, and MENG Xu
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  • [in Chinese]
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    References(10)

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    [8] [8] BAE W, JU H, PARK K, et al. A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2016, 51(10): 2357-2367.

    [9] [9] NIRMALRAJ T, RADHAKRISHNAN S, KARN R K, et al. Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology [C]// IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI). Chennai, India. 2017: 1074-1076.

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    GONG Hao, WANG Xiaolei, ZHOU Min, MENG Xu. A Low Power Multi-Phase Clock Generation Circuit for TDC[J]. Microelectronics, 2023, 53(5): 846

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    Paper Information

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    Received: Mar. 14, 2023

    Accepted: --

    Published Online: Jan. 3, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230107

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