[2] [2] MUER B D, STEYAERT M. On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity ［J］. IEEE Trans Circ Syst II Analog & Digital Signal Proces, 2003, 50(11): 784-793.

[3] [3] LIANG C, WANG P. A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter ［C］// IEEE ISSCC. San Francisco, CA, USA. 2015: 1-3.

[4] [4] NANDWANA R K, ANAND T, SAXENA S, et al. A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method ［J］. IEEE J Sol Sta Circ, 2015, 50(4): 882-895.

[5] [5] JEE D, SUH Y, KIM B, et al. A FIR-embedded phase interpolator based noise filtering for wide-bandwidth fractional-N PLL ［J］. IEEE J Sol Sta Circ, 2013, 48(11): 2795-2804.

[6] [6] LEVANTINO S, MARZIN G, SAMORI C, et al. A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration ［J］. IEEE J Sol Sta Circ, 2013, 48(10): 2419-2429.

[7] [7] PARK D, CHO S. A 14.2 mW 2.55-to-3 GHz cascaded PLL with reference injection and 800 MHz delta-sigma modulator in 0.13 μm CMOS ［J］. IEEE J Sol Sta Circ, 2012, 47(12): 2989-2998.

[8] [8] MENG X, ZHOU L, LIN F, et al. A low-noise digital-to-frequency converter based on injection- locked ring oscillator and rotated phase selection for fractional-N frequency synthesis ［J］. IEEE Trans VLSI Syst, 2019, 27(6): 1378-1389.

[9] [9] GAO X, KLUMPERINK E A M, GERAEDTS P F J, et al. Jitter analysis and a benchmarking figure-of-merit for phase-locked loops ［J］. IEEE Trans Circ Syst II: Expr Brie, 2009, 56(2): 117-121.

[10] [10] LEE J S, KEEL M S, KIM S, et al. Charge pump with perfect current matching characteristics in phase-locked loops ［J］. Elec Lett, 2000, 36(23): 1907-1908.

[11] [11] SHI X, IMFELD K, TANNER S, et al. A low-jitter and low-power CMOS PLL for clock multiplication ［C］// Proceed 32nd ESSCIRC. Montreux, Switzerland. 2006: 174-177.