Microelectronics, Volume. 53, Issue 5, 841(2023)
Design of a Buffer Optimization Architecture for ZynqNet Hardware Accelerator
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CHEN Zhuo, CHEN Yiduo, TIAN Chunsheng, QIU Peiyi, DI Zhixiong. Design of a Buffer Optimization Architecture for ZynqNet Hardware Accelerator[J]. Microelectronics, 2023, 53(5): 841
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Received: Mar. 4, 2023
Accepted: --
Published Online: Jan. 3, 2024
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