Journal of Terahertz Science and Electronic Information Technology , Volume. 21, Issue 8, 1059(2023)

A high-speed adjustable model of digital Low Drop Out regulators based on PI controller

LYU Shengping, GENG Jiarong*, ZHANG Hongda, and CHEN Zhijie
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    References(10)

    [1] [1] MAGOD R, SUDA N, IVANOV V, et al. A low-noise output capacitorless low-dropout regulator with a switched-RC bandgap reference[J]. IEEE Transactions on Power Electronics, 2017,32(4):2856-2864.

    [2] [2] LU Yan,KI Winghung,PATRICK YUE C. 17.11 A 0.65 ns-response-time 3.01 ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems[C]// IEEE International Solid-State Circuits Conference Digest of Technical Papers(ISSCC). San Francisco,CA:IEEE, 2014:306-307.

    [3] [3] OKUMA Y,ISHIDA K,RYU Y,et al. 0.5 V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS[C]// IEEE Custom Integrated Circuits Conference 2010(CICC). San Jose,CA:IEEE, 2010:1-4.

    [4] [4] SAMANTAK G,YOUNGTAK L,SAAD B N,et al. Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads[C]// Design,Automation & Test in Europe Conference & Exhibition (DATE). Dresden,Germany:IEEE, 2014:1-6.

    [5] [5] JIAYOON Z R, CLAUDIA P, PAUL G, et al. A high-linearity digital-to-time converter technique: constant-slope charging[J]. IEEE Journal of Solid-State Circuits, 2015,50(6):1412-1423.

    [6] [6] HANLI L, DEXIAN T, ZHENG S, et al. A sub-mW fractional-N ADPLL with FOM of.246 dB for iot applications[J]. IEEE Journal of Solid-State Circuits, 2018,53(12):3540-3552.

    [7] [7] HANLI L, DEXIAN T, ZHENG S, et al. A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246 dB for iot applications in 65 nm CMOS[C]// IEEE International Solid-State Circuits Conference(ISSCC). San Francisco, CA,USA:IEEE, 2018:246-248.

    [9] [9] OTSUGA K,ONOUCHI M,IGARASHI Y,et al. An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor[C]// IEEE International SOC Conference. Niagara Falls,NY:IEEE, 2012:11-14.

    [12] [12] LIM C Y,MANDAL D,BAKKALOGLU B,et al. A 50 mA 99.2% peak current efficiency, 250 ns settling time digital low-dropout regulator with transient enhanced PI controller[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2017,25 (8):2360-2370.

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    LYU Shengping, GENG Jiarong, ZHANG Hongda, CHEN Zhijie. A high-speed adjustable model of digital Low Drop Out regulators based on PI controller[J]. Journal of Terahertz Science and Electronic Information Technology , 2023, 21(8): 1059

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    Paper Information

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    Received: Apr. 17, 2021

    Accepted: --

    Published Online: Jan. 17, 2024

    The Author Email: Jiarong GENG (wdzhuanye12@emails.bjut.edu.cn)

    DOI:10.11805/tkyda2021159

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