An innovative 10-bit segmented current-steering digital-to-analog converter (DAC) was designed through an SMIC 180 nm standard CMOS process, utilizing a minimalistic footprint of 320 μm×150 μm. The "5+5" segmentation architecture achieves a high-position quantization ladder of the DAC through resistors, thus minimizing the total current. Compared with the original resistance quantization structure, this innovative structure alters the current flow direction, conserving half the current sources. Furthermore, the distinct non-ideal characteristics inherent in this novel structure are rectified effectively using a calibration method, traditionally employed in resistor string DACs. Simulation results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) of the DAC are confined to 0.09 and 0.34 LSB, respectively, while achieving a spur-free dynamic range of 64.52 dB and a power consumption of 8.58 mW. Compared with conventional structures, this structure demonstrates an approximate 80% reduction in the area consumption and mitigates the power and area of the segmented current-steering DAC.