Electronics Optics & Control, Volume. 23, Issue 8, 85(2016)

Implementation of DDR3 Controller in High-Speed Image Compression System

CHEN Zhan-liang1...2, JIN Long-xu1, TAO Hong-jiang1 and HAN Shuang-li1 |Show fewer author(s)
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    References(5)

    [4] [4] PAN G T, LUO L, OU G D. Design and implementation of a DDR3-based memory controller[C]//Third International Conference on Intelligent System Design and Engineering Applications, 2013: 540-543.

    [5] [5] LSLAM M A, ARAFATH M Y, HASAN M J. Design of DDR4 SDRAM controller[C]//8th International Conference on Electrical and Computer Engineering, Dhaka, Bangladesh, 2014: 148-151.

    [6] [6] Xilinx. Spartan-6 FPGA memory interface solutions[EB/OL]. [2010-09-21]. http: //www. xilinx. com.

    [10] [10] Xilinx. Spartan-6 FPGA memory controller[EB/OL]. [2010-08-09]. http: //www. xilinx. com.

    [11] [11] CHEN H M, MA S, WANG L. A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller[J]. Science China(Information Sciences), 2014, 57(12): 176-183.

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    CHEN Zhan-liang, JIN Long-xu, TAO Hong-jiang, HAN Shuang-li. Implementation of DDR3 Controller in High-Speed Image Compression System[J]. Electronics Optics & Control, 2016, 23(8): 85

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    Paper Information

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    Received: May. 15, 2015

    Accepted: --

    Published Online: Jan. 27, 2021

    The Author Email:

    DOI:10.3969/j.issn.1671-637x.2016.08.020

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