Journal of Terahertz Science and Electronic Information Technology , Volume. 19, Issue 2, 338(2021)

Design of a single event effects hardened input interface circuit

GUAN Xiaoming*, FANG Jian, LAI Rongxing, and LUO Yunzhong
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    References(6)

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    [5] [5] SHAH J S,SACHDEV M. Radiation hardened pulsed latches in 65 nm CMOS[C]// IEEE Canadian Conference on Electrical and Computer Engineering(CCECE). [S.1.]:IEEE, 2016:1-4.

    [6] [6] TADROS R N,HUA W Z,MOREORA M T,et al. A low power low-area error-detecting latch for resilient architectures in 28 nm FDSOI[J]. IEEE Transactions on Circuits and SystemsⅡ:Express Brief, 2016,63(9):858-862.

    [7] [7] UENO H,NAMBA K. Construction of a Soft Error(SEU) hardened latch with high critical charge[C]// IEEE International Symposium on Defect and Fault Tolerance(DFT) in VLSI and Nanotechnology Systems. [S.1.]:IEEE, 2016:27-30.

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    GUAN Xiaoming, FANG Jian, LAI Rongxing, LUO Yunzhong. Design of a single event effects hardened input interface circuit[J]. Journal of Terahertz Science and Electronic Information Technology , 2021, 19(2): 338

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    Paper Information

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    Received: Dec. 9, 2019

    Accepted: --

    Published Online: Jul. 16, 2021

    The Author Email: Xiaoming GUAN (523557479@qq.com)

    DOI:10.11805/tkyda2019526

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