Chinese Journal of Quantum Electronics, Volume. 20, Issue 5, 613(2003)

High-efficiency Two-phase CMOS High Voltage Generator

[in Chinese]1, [in Chinese]1, [in Chinese]2, [in Chinese]2, and [in Chinese]1
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  • 2[in Chinese]
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    References(5)

    [1] [1] Toru T, Tomoharu T. A dynamic analysis of the Dickson charge pump circuit [J]. IEEE J. Solid-State Circuits,1997, 32(8): 1231-1240

    [2] [2] Dickson J F. On-chip high-voltage generation in MNOS integrated circuit using an improved voltage multiplier technique [J]. IEEE J. Solid-State Circuits, 1976, SC-11(3): 374-378

    [3] [3] Behzad R. Design of Analog CMOS Integrated Circuit [M]. MeGraw-Hill, 2000.

    [4] [4] Witters J S, Groeseneken G, Herman E M. Analysis and modeling of on- chip high-voltage generator circuits for use in EEPROM circuits [J]. EEE J. Solid-State Circuits, 1989, 24(5): 592-597

    [5] [5] Akira U, et al. A 5 V-only operation 0.6μm flash EEPROM with row decoder scheme in triple-well structure [J].IEEE J. Solid-State Circuits, 1998, 27(11)

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    [in Chinese], [in Chinese], [in Chinese], [in Chinese], [in Chinese]. High-efficiency Two-phase CMOS High Voltage Generator[J]. Chinese Journal of Quantum Electronics, 2003, 20(5): 613

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    Paper Information

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    Received: Sep. 24, 2002

    Accepted: --

    Published Online: May. 15, 2006

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