Fig. 1. Schematic diagram of chip structure

Fig. 2. Schematic diagram of multi band splicing

Fig. 3. Diagram of Dewar structure

Fig. 4. Schematic diagram of the flatness adjustment mechanism for dual band detectors

Fig. 5. Schematic diagram of three-dimensional adjustment of detector module

Fig. 6. Flow chart of detector module adjustment

Fig. 7. Thermal layer structure design for 40 K temperature zone

Fig. 8. Low temperature stress under different thermal layer structures

Fig. 9. Low temperature stress under different thermal layer structures

Fig. 10. Low temperature stress under different thermal layer structures

Fig. 11. Low temperature deformation of detector diagonal distance

Fig. 12. Temperature gradient verification principle and thermal network model. (a) Temperature gradient verification principle; (b) The figure of thermal network model

Fig. 13. Temperature gradient verification test

Fig. 14. Temperature gradient verification test

Fig. 15. Filter holder support structure and low temperature deformation test of filter. (a) Filter holder support structure; (b) Low temperature deformation testing device for optical filters

Fig. 16. Photo of Dewar