Fig. 1. Programmability comparisons among different chips.

Fig. 2. An architecture model of reconfigurable computing.

Fig. 3. The structure of RCC.

Fig. 4. The structure of RCD.

Fig. 5. The structures of PEA and a PE.

Fig. 6. The architecture of HReA.

Fig. 7. Example of dividing and executing a kernel.

Fig. 8. The compiler framework of a reconfigurable processor.

Fig. 9. Temporal partition of task graph.

Fig. 10. Illustration of internal memory management. (a) Multiple output targets. (b) Communication between subtasks.