Microelectronics, Volume. 53, Issue 1, 134(2023)
A Triple-RESURF LDMOS with Segmented P Buried Layer
[1] [1] LADHANI H, MAALOUF E, JONES J K, et al. A compact, 42% PAE, two-stage, LDMOS Doherty PA module for massive MIMO applications [C] // IEEE MTT-S Int Microw Conf Hardware Syst for 5G & Beyond. Atlanta, GA, USA. 2019: 1-3.
[2] [2] PARK S, JANG K, KIM B, et al. Experiments on a 80 kW power combiner using RF LDMOS power transistors [C] // IEEE Asia-Pacific Microw Conf. Kyoto, Japan: 2018: 141-143.
[3] [3] PARK I Y, SALAMA C A T. CMOS compatible super junction LDMOST with N-buffer layer [C] // Proceed 17th Int Symp Power Semicond Dev & ICs. Santa Barbara, CA, USA. 2005: 163-166.
[4] [4] WU L J, YANG H, WU Y Q, et al. A novel superjunction lateral double-diffused MOS with segmented buried P-layer [J]. Superlattices Microstruct, 2018, 116: 262-268.
[5] [5] HE N L, ZHANG S, ZHU X H, et al. A 0.25 μm 700 V BCD technology with ultra-low specific on-resistance SJ-LDMOS [C] // Proceed 32th Int Symp Power Semicond Dev & ICs. Vienna, Austria. 2020: 419-422.
[6] [6] ZHANG J, GUO Y, YAO J, et al. A new RESURF model based on sharing charge gradual apportionment concept for lateral power devices [C] // IEEE Int Conf Elec Dev & Sol Sta Circ. Singapore. 2015: 637-640.
[7] [7] QIAO M, WANG Y R, ZHOU X, et al. Analytical modeling for a novel triple RESURF LDMOS with N-top layer [J]. IEEE Trans Elec Dev, 2015, 62(9): 2933-2939.
[8] [8] ZHANG S D, SIN J, LAI T, et al. Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices [J]. IEEE Trans Elect Dev, 1999, 46(5): 1036-1041.
[9] [9] LI Y, QIAO M, JIANG Y, et al. Uniform and linear variable doping ultra-thin PSOI LDMOS with n-type buried layer [J]. Elec Lett, 2013, 49(22): 1407-1409.
[10] [10] IQBAL M H, UDREA F, NAPOLI E. On the static performance of the RESURF LDMOSFETS for power ICs [C] // Proceed 21th Int Symp Power Semicond Dev & ICs. Barcelona, Spain. 2009: 247-250.
[11] [11] CHENG S K, FANG D, QIAO M, et al. A novel 700 V deep trench isolated double RESURF LDMOS with P-sink layer [C] // Proceed 29th Int Symp Power Semicond Dev & ICs. Sapporo, Japan. 2017: 323-326.
[12] [12] KIM S, KIM J, PROSACK H. Novel lateral 700 V DMOS for integration: ultra-low 85 mΩ·cm2 on-resistance, 750 V LFCC [C] // Proceed 24th Int Symp Power Semicond Dev & ICs. Bruges, Belgium. 2017: 185-188.
[13] [13] QIAO M, YUAN Z Y, LI Y, et al. Suppression of hot-hole injection in high-voltage triple RESURF LDMOS with sandwich N-P-N layer: toward high-performance and high-reliability [C] // Proceed 32th Int Symp Power Semicond Dev & ICs. Vienna, Austria. 2020: 415-418.
[14] [14] QIAO M, LI Y F, ZHOU X, et al. A 700 V junction-isolated triple RESURF LDMOS with N-type top layer [J]. Elec Lett, 2014, 35(7): 774-776.
Get Citation
Copy Citation Text
HE Nailong, XU Jie, WANG Hao, ZHAO Jingchuan, WANG Ting, ZHU Wenming, ZHANG Sen. A Triple-RESURF LDMOS with Segmented P Buried Layer[J]. Microelectronics, 2023, 53(1): 134
Category:
Received: Jan. 31, 2022
Accepted: --
Published Online: Dec. 15, 2023
The Author Email: