Microelectronics, Volume. 52, Issue 5, 915(2022)

Study on ESD Protection Performance of Gated Diode in 14 nm FinFET Process

WANG Jun
Author Affiliations
  • [in Chinese]
  • show less
    References(10)

    [1] [1] OKANO K, IZUMIDA T, KAWASAKI H, et al. Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length [C]// IEEE Int Elec Dev Meet. 2005: 721-724.

    [2] [2] RUSS C. ESD issues in advanced CMOS bulk and FinFET technologies: processing, protection devices and circuit strategies [J]. Microelec Reliab, 2008, 48 (8-9): 1403-1411.

    [3] [3] CHEN S H, LINTEN D, LEE J W, et al. Gated and STI defined ESD diodes in advanced bulk FinFET technologies [C]// IEEE Int Elec Dev Meet. 2014: 20.4.1-20.4.4.

    [4] [4] CHEN S H, LINTEN D, SCHOLZ M, et al. VFTLP characteristics of ESD protection diodes in advanced bulk FinFET technology [C]// 37th EOS/ESD. 2015: 1-6.

    [5] [5] CHEN S H, LINTEN D, HELLINGS G, et al. Transient overshoot of sub-10 nm bulk FinFET ESD diodes with S/D epitaxy stressor [C]// 41st EOS/ESD. 2019: 1-8.

    [6] [6] LINTEN D, HELLINGS G, CHEN S, et al. ESD in FinFET technologies: past learning and emerging challenges [C]// IEEE Int Reliab Phys Symp. 2013: 2B.5.1-2B.5.8.

    [7] [7] CHEN S H, HELLINGS G, THIJS S, et al. Process options impact on ESD diode performance in bulk FinFET technology [J]. IEEE Trans Elec Dev, 2016, 63 (9): 3424-3431.

    [8] [8] LI Y, MIAO M, GAUTHIER R. Design and optimization of ESD P-direction diode in bulk FinFET technology [C]// 40th EOS/ESD. 2018: 1-7.

    [9] [9] KHAZHINSKY M G, CHOWDHURY M M, TEKLEAB D, et al. Study of undoped channel FinFETs in active rail clamp ESD networks [C]// IEEE Int Reliab Phys Symp. 2008: 262-269.

    [10] [10] WU W M, KER M D, CHEN S H, et al. RF/high-speed I/O ESD protection: co-optimizing strategy between BEOL capacitance and HBM immunity in advanced CMOS process [J]. IEEE Trans Elec Dev, 2020, 67(7): 2752-2759.

    Tools

    Get Citation

    Copy Citation Text

    WANG Jun. Study on ESD Protection Performance of Gated Diode in 14 nm FinFET Process[J]. Microelectronics, 2022, 52(5): 915

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: May. 3, 2022

    Accepted: --

    Published Online: Jan. 18, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220153

    Topics