Microelectronics, Volume. 52, Issue 5, 837(2022)

Design of a LDO Circuit with Low Noise and High Power Suppression

WANG Yan1...2, YANG Xiaoyu1,2, WEI Ling1,2, and ZHAO Zhiyu12 |Show fewer author(s)
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  • 1[in Chinese]
  • 2[in Chinese]
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    References(3)

    [1] [1] LAVALLEAVILES F, TOMES J, SANCHEZ-SINENCIO E, et al. A high power supply rejection and fast settling time capacitor-less LDO [J]. IEEE Trans Power Elec, 2019, 34(1): 474-484.

    [11] [11] SANTRA A, KHAN Q A. A power efficient output capacitor-less LDO regulator with auto-low power mode and using feed-forward compensation [C]// 32nd Int Conf VLSID. Delhi, India. 2019: 36-40.

    [12] [12] WANG L, MAO W, WU C D, et al. A fast transient LDO based on dual loop FVF with high PSR [C]// IEEE AAPCCAS. Jeju, South Korea. 2016: 99-102.

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    WANG Yan, YANG Xiaoyu, WEI Ling, ZHAO Zhiyu. Design of a LDO Circuit with Low Noise and High Power Suppression[J]. Microelectronics, 2022, 52(5): 837

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    Paper Information

    Special Issue:

    Received: May. 3, 2022

    Accepted: --

    Published Online: Jan. 18, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.220152

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